DSP56309UM Datasheet, PDF (225/424 Pages) Motorola, Inc – 24-Bit Digital Signal Processor

Freescale Semiconductor, Inc.
Serial Communication Interface (SCI)
SCI Programming Model
8.3.2.7
SSR Framing Error Flag (FE) Bit 6
The FE bit is set in asynchronous modes when no stop bit is detected in the data string
received. FE and RDRE are set simultaneously when the received word is transferred to
the SRX. However, the FE flag inhibits further transfer of data into the SRX until it is
cleared. FE is cleared when the SCI status register is read followed by reading the SRX. A
hardware RESET signal, software RESET instruction, SCI individual reset, or STOP
instruction also clears FE. In 8-bit synchronous mode, FE is always cleared. If the byte
received causes both framing and overrun errors, the SCI receiver recognizes only the
overrun error.
8.3.2.8
SSR Received Bit 8 (R8) Address Bit 7
In 11-bit asynchronous multidrop mode, the R8 bit is used to indicate whether the
received byte is an address or data. R8 is set for addresses and is cleared for data. R8 is
not affected by reading the SRX or SCI status register. A hardware RESET signal,
software RESET instruction, SCI individual reset, or STOP instruction also clears R8.
8.3.3 SCI Clock Control Register (SCCR)
The SCCR is a 24-bit, read/write register that controls the selection of the clock modes
and baud rates for the transmit and receive sections of the SCI interface. The control bits
are described in the following paragraphs. The SCCR is cleared by a hardware RESET
signal. The basic features of the clock generator (as in Figure 8-5 on page 8-16 and
Figure 8-6 on page 8-18) are these:
¥ The SCI logic always uses a 16 ´ internal clock in asynchronous modes and
always uses a 2 ´ internal clock in synchronous mode. The maximum internal
clock available to the SCI peripheral block is the oscillator frequency divided by 4.
¥ The 16 ´ clock is necessary for asynchronous modes to synchronize the SCI to the
incoming data, as in Figure 8-5.
¥ For asynchronous modes, the user must provide a 16 ´ clock to use an external
baud rate generator (i.e., SCLK input).
¥ For asynchronous modes, the user can select either 1 ´ or 16 ´ for the output clock
when using internal TX and RX clocks (TCM = 0 and RCM = 0).
Â¥ When SCKP is cleared, the transmitted data on the TXD signal changes on the
negative edge of the 1 ´ serial clock and is stable on the positive edge. When
SCKP is set, the data changes on the positive edge and is stable on the negative
edge.
Â¥ The received data on the RXD signal is sampled on the positive edge (if SCKP = 0)
or on the negative edge (if SCKP = 1) of the 1 ´ serial clock.
MOTOROLA
DSP56309UM/D
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