MC88915FN70 Datasheet, PDF (6/13 Pages) Motorola, Inc – Low Skew CMOS PLL Clock Driver

MC88915
EXTERNAL LOOP FILTER ^RC1
330Ω _R2
0.1µF
C1
470KΩ
REFERENCE
RESISTOR
ANALOG GND
With the 470KΩ resistor tied in this fashion, the tPD specification
measured at the input pins is:
tPD = 2.25ns ± 1.0ns
SYNC INPUT
2.25ns OFFSET
FEEDBACK OUTPUT
3.0V
5.0V
ANALOG VCC
470KΩ
REFERENCE
RC1
RESISTOR _{330Ω R2}
0.1µF
C1
ANALOG GND
With the 470KΩ resistor tied in this fashion, the tPD specification
measured at the input pins is:
tPD = –0.775ns ± 0.275ns
SYNC INPUT
FEEDBACK OUTPUT
3.0V
–0.775ns OFFSET
5.0V
Figure 2. Depiction of the Fixed SYNC to Feedback Offset (tPD) Which is
Present When a 470KΩ Resistor is Tied to VCC or Ground
5. ThetSKEWrspecificationguaranteesthattherisingedges
of outputs Q/2, Q0, Q1, Q2, Q3, and Q4 will always fall
within a 500ps window within one part. However, if the
relative position of each output within this window is not
specified, the 500 ps window must be added to each side
of the tPD specification limits to calculate the total
part–to–part skew. For this reason the absolute
distribution of these outputs are provided in table 2. When
taking the skew data, Q0 was used as a reference, so all
measurements are relative to this output. The information
in Table 2 is derived from measurements taken from the
14 process lots described in Note 1, over the temperature
and voltage range.
–
+
Output
(ps)
(ps)
Q0
0
0
Q1
–72
40
Q2
–44
276
Q3
–40
255
Q4
–274
–34
Q/2
–16
250
2X_Q
–633
–35
Table 2. Relative Positions of Outputs Q/2, Q0–Q4, 2X_Q, Within the 500ps tSKEWr Spec Window
MOTOROLA
6
TIMING SOLUTIONS
BR1333 — Rev 6