MC88915FN70 Datasheet, PDF (5/13 Pages) Motorola, Inc – Low Skew CMOS PLL Clock Driver

MC88915
General AC Specification Notes
1. Several specifications can only be measured when the
MC88915 is in phase–locked operation. It is not possible
to have the part in phase–lock on ATE (automated test
equipment). Statistical characterization techniques were
used to guarantee those specifications which cannot be
measured on the ATE. MC88915 units were fabricated
with key transistor properties intentionally varied to
create a 14 cell designed experimental matrix. IC
performance was characterized over a range of transistor
properties (represented by the 14 cells) in excess of the
expected process variation of the wafer fabrication area.
Response Surface Modeling (RSM) techniques were
used to relate IC performance to the CMOS transistor
properties over operation voltage and temperature. IC
Performance to each specification and fab variation were
used in conjunction with Yield Surface Modeling™ (YSM
™) methodology to set performance limits of ATE testable
specifications within those which are to be guaranteed by
statistical characterization. In this way all units passing
the ATE test will meet or exceed the non–tested
specifications limits.
2. These two specs (tRlSE/FALL and tPULSE Width 2X_Q
output) guarantee that the MC88915 meets the 25 MHz
68040 P–Clock input specification (at 50 MHz). For these
two specs to be guaranteed by Motorola, the termination
scheme shown below in Figure 1 must be used.
3. The wiring Diagrams and written explanations in Figure 5
demonstrate the input and output frequency relationships
for three possible feedback configurations. The allowable
SYNC input range for each case is also indicated. There
are two allowable SYNC frequency ranges, depending
whether FREQ_SEL is high or low. Although not shown, it
is possible to feed back the Q5 output, thus creating a
180° phase shift between the SYNC input and the “Q”
outputs. Table 1 below summarizes the allowable SYNC
frequency range for each possible configuration.
88915
2X_Q
Output
Rs
ZO (CLOCK TRACE)
Rs = Zo – 7 Ω
Rp
68040
P–Clock
Input
Rp = 1.5 Zo
Figure 1. MC68040 P–Clock Input Termination Scheme
FREQ_SEL
Level
Feedback
Output
Allowable SYNC Input
Frequency Range (MHZ)
HIGH
HIGH
HIGH
HIGH
LOW
LOW
LOW
LOW
Q/2
Any “Q” (Q0–Q4)
Q5
2X_Q
Q/2
Any “Q” (Q0–Q4)
Q5
2X_Q
5 to (2X_Q FMAX Spec)/4
10 to (2X_Q FMAX Spec)/2
10 to (2X_Q FMAX Spec)/2
20 to (2X_Q FMAX Spec)
2.5 to (2X_Q FMAX Spec)/8
5 to (2X_Q FMAX Spec)/4
5 to (2X_Q FMAX Spec)/4
10 to (2X_Q FMAX Spec)/2
Corresponding VCO
Frequency Range
20 to (2X_Q FMAX Spec)
20 to (2X_Q FMAX Spec)
20 to (2X_Q FMAX Spec)
20 to (2X_Q FMAX Spec)
20 to (2X_Q FMAX Spec)
20 to (2X_Q FMAX Spec)
20 to (2X_Q FMAXSpec)
20 to (2X_Q FMAXSpec)
Phase Relationships
of the “Q” Outputs
to Rising SYNC Edge
0°
0°
180°
0°
0°
0°
180°
0°
Table 1. Allowable SYNC Input Frequency Ranges for Different Feedback Configurations.
4. A 1 MΩ resistor tied to either Analog VCC or Analog GND
as shown in Figure 2 is required to ensure no jitter is
present on the MC88915 outputs. This technique causes
a phase offset between the SYNC input and the output
connected to the FEEDBACK input, measured at the
input pins. The tPD spec describes how this offset varies
with process, temperature, and voltage. The specs were
arrived at by measuring the phase relationship for the 14
lots described in note 1 while the part was in
phase–locked operation. The actual measurements were
made with a 10 MHz SYNC input (1.0 ns edge rate from
0.8 V – 2.0 V) with the Q/2 output fed back. The phase
measurements were made at 1.5 V. The Q/2 output was
terminated at the FEEDBACK input with 100Ω to VCC and
100 Ω to ground.
TIMING SOLUTIONS
5
BR1333 — Rev 6
MOTOROLA