MC88915FN70 Datasheet, PDF (11/13 Pages) Motorola, Inc – Low Skew CMOS PLL Clock Driver

MC88915
CLOCK
@f
SYSTEM
CLOCK
SOURCE
DISTRIBUTE
CLOCK @ f
CLOCK @ 2f
AT POINT OF USE
MC88915
PLL
2f
CMMU CMMU
CPU CMMU
CMMU CMMU
MC88915
PLL
2f
CMMU CMMU
CPU ^CMMU
CMMU CMMU
CPU
CARD
CPU
CARD
PLL
2f
MEMORY
CONTROL
MEMORY
CARDS
CLOCK @ 2f
AT POINT OF USE
Figure 7. Representation of a Potential Multi–Processing Application Utilizing the MC88915
for Frequency Multiplication and Low Board–to–Board Skew
MC88915 System Level Testing Functionality
When the PLL_EN pin is low, the VCO is disabled and the 88915 is in low frequency “test mode”. In test mode (with FREQ_SEL
high), the 2X_Q output is inverted from the selected SYNC input, and the “Q” outputs are divide–by–2 (negative edge triggered)
of the SYNC input, and the Q/2 output is divide–by–4. With FREQ_SEL low the 2X_Q output is divide–by–2 of the SYNC, the “Q”
outputs divide–by–4, and the Q/2 output divide–by–8. These relationships can be seen on the block diagram. A recommended
test configuration would be to use SYNC0 as the test clock input, and tie PLL_EN and REF_SEL together and connect them to
the test select logic. When these inputs are low, the 88915 is in test mode and the SYNC0 input is selected.
This functionality is needed since most board–level testers run at 1 MHz or below, and the 88915 cannot lock onto that low of an
input frequency. In the test mode described above, any frequency test signal can be used.
TIMING SOLUTIONS
11
BR1333 — Rev 6
MOTOROLA