MC88915FN70 Datasheet, PDF (2/13 Pages) Motorola, Inc – Low Skew CMOS PLL Clock Driver

MC88915
FEEDBACK
SYNC (0)
0
M
U
SYNC (1)
X
1
REF_SEL
PHASE/FREQ.
DETECTOR
LOCK
CHARGE PUMP/LOOP
FILTER
VOLTAGE
CONTROLLED
OSCILLATOR
EXTERNAL REC NETWORK
(RC1 Pin)
PLL_EN
0
1
MUX
(÷1)
(÷2)
DIVIDE
BY TWO
1
M
U
X
0
FREQ_SEL
RST
PIN SUMMARY
Pin Name Num I/O
Function
SYNC[0]
1 Input Reference clock input
SYNC[1]
1 Input Reference clock input
REF_SEL
1 _Input Chooses reference between sync[0] & Sync[1]
FREQ_SEL 1 Input Selects Q output frequency
FEEDBACK 1 Input Feedback input to phase detector
RC1
1 _Input Input for external RC network
Q(0–4)
5 _Output Clock output (locked to sync)
Q5
1 _Output Inverse of clock output
2x_Q
1 _Output 2 x clock output (Q) frequency (synchronous)
Q/2
1 _Output Clock output(Q) frequency ÷ 2 (synchronous)
LOCK
1 _Output Indicates phase lock has been achieved (high when locked)
RST
1 _Input Asynchronous reset (active low)
PLL_EN
1 _Input Disables phase–lock for low freq. testing
VCC,GND
11
Power and ground pins (note pins 8, 10 are
“quiet” supply pins for internal logic only)
2x_Q
DQ
Q0
CP _Q
R
DQ
Q1
CP
R
DQ
Q2
CP
R
DQ
Q3
CP
R
DQ
Q4
CP
R
DQ
Q5
CP
R
MOTOROLA
MC88915 Block Diagram
2
DQ
Q/2
CP
R
TIMING SOLUTIONS
BR1333 — Rev 6