MC88915FN70 Datasheet, PDF (4/13 Pages) Motorola, Inc – Low Skew CMOS PLL Clock Driver

MC88915
AC ELECTRICAL CHARACTERISTICS (TA =0° C to +70° C, VCC = 5.0V ±5%, CL = 50pF)
Symbol
Parameter
Min
Max
Unit
tRISE, tFALL Rise and Fall Times, all Outputs Into a 50 pF, 500 Ω Load
1.0
(Outputs)
(Between 0.2VCC and 0.8VCC)
tRISE, tFALL ³ Rise and Fall Time, 2X_Q Output Into a 20 pF Load With Termina-
0.5
(2X_Q Output) tion specified in note 2 (Between 0.8 V and 2.0 V)
2.5
ns
1.6
ns
tPulse _Width ³ Output Pulse Width (Q0, Q1, Q3, Q4, Q5, Q/2 @VCC/2)
0.5tCYCLE – 0.5 0.5tCYCLE + 0.5
(Q0,Q1,Q3,Q4,
Q5,Q/2)
tCYCLE = 1/Freq. at which the “Q”
tPulse _Width ³
(Q2 only)
tPulse _Width ³
(2X_Q Output)
tPulse _Width ³
(2X_Q Output)
tPD ³
(Sync–Feedback)
Output Pulse Width (Q2 Output @ VCC/2)
Output Pulse Width (2X_Q Output @ 1.5 V) (See AC Note 2)
Output Pulse Width (2X_Q Output @ VCC/2)
SYNC input to feedback delay
Outputs are running
ns
0.5tCYCLE – 0.6 0.5tCYCLE + 0.6
0.5tCYCLE – 0.5 0.5tCYCLE + 0.5 ns
0.5tCYCLE – 1.0 0.5tCYCLE + 1.0 ns
(470kΩ From RC1 to An.VCC)
–1.05
–0.50
(meas. @ SYNC0 or 1 and FEEDBACK input pins)
(470kΩ From RC1 to An.GND)
ns
tSKEWr ^1,3
(Rising)
tSKEWf ^1,3
(Falling)
tSKEWall ^1,3
tLOCK
(See General AC Specification note 4 and Fig. 2 for explanation)
Output–to–Output Skew Between Outputs Q0 – Q4, Q/2
(Rising Edges Only)
Output–to–Output Skew Between Outputs Q0 – Q4
(Falling Edges Only)
Output–to–Output Skew Between Outputs 2X_Q, Q/2, Q0 – Q4
Rising, Q5 Falling
Time Required to acquire ² Phase–Lock from time SYNC Input Sig-
nal is Received.
+1.25
–
–
–
1
+3.25
500
ps
750
ps
750
ps
10
ms
tPHL
(Reset – Q)
Propagation Delay, RST to Any Output (High–Low)
1.5
13.5
ns
1. Under equally loaded conditions, CL ≤50pF (±2pF), and at a fixed temperature and voltage.
2. With VCC fully powered–on and an output properly connected to the FEEDBACK pin. tLOCK Max. is with C1 = 0.1µF, tLOCK Min is with
C1 = 0.01µF.
3. These specifications are not tested, they are guaranteed by statistical characterization. See General AC Specification note 1.
RESET TIMING REQUIREMENTS ¹
Symbol
Parameter
Minimum
Unit
tREC, RST
Reset Recovery Time rising RST
9.0
ns
to SYNC
edge to falling SYNC edge
tW, RST
Minimum Pulse Width,
5.0
ns
LOW
RST input LOW
1. These reset specs are valid only when PLL_EN is LOW and the part is in Test mode (not in phase–lock)
MOTOROLA
4
TIMING SOLUTIONS
BR1333 — Rev 6