MC145574 Datasheet, PDF (130/164 Pages) Motorola, Inc – ISDN S/T-Interface Transceiver

Freescale Semiconductor, Inc.
18.7 SCP TIMING CHARACTERISTICS
(TA = – 40 to + 85°C, VDD = 5.0 V ± 5%, Voltages Referenced to VSS)
Ref. No.
Characteristic
Min
Max
Unit
12
SCPEN Active Before Rising Edge of SCPCLK
50
—
ns
13
SCP Rising Edge Before SCPEN Active
50
—
ns
14
SCP Rx Valid Before SCPCLK Rising Edge (Setup Time)
20
—
ns
15
SCP Rx Valid After SCPCLK Rising Edge (Hold Time)
20
—
ns
16
SCPCLK Period (Note 1)
244
—
ns
17
SCPCLK Width (Low)
30
—
ns
18
SCPCLK Width (High)
30
—
ns
19
SCP Tx Active Delay
—
50
ns
20
SCPEN Active to SCP Tx Active
—
50
ns
21
SCPCLK Falling Edge to SCP Tx High–Impedance
—
40
ns
22
SCPEN Inactive Before SCPCLK Rising Edge
50
—
ns
23
SCPCLK Rising Edge Before SCPEN Inactive
50
—
ns
24
SCPCLK Falling Edge to SCP Tx Valid Data
NOTE:
1. Maximum SCP Clock Frequency is 4.096 MHz.
—
50
ns
SCP EN
12
13
16
22
23
SCPCLK
1
2
3
4
5
6
7
8
18
15
21
14
17
SCP Rx
(NOTE 1)
19
SCP Tx
(NOTE 2)
24
SCP Rx
(NOTE 3)
20
SCP Tx
(NOTE 3)
NOTES:
1. During a nibble read, four bits are presented on SCP Rx.
2. During a nibble read, SCP Tx will be active for the duration of the 4–bit transmission as shown.
3. During a byte read, eight bits are presented on SCP Rx. A byte transaction consists of two 8–bit ex-
changes. During the second 8–bit exchange, data is either written to the byte from SCP Rx or is read
from the byte. If the operation is a read operation, then data is presented onto SCP Tx. Refer to Section 5,
“The Serial Control Port”, for a detailed description.
Figure 18–4. SCP Timing Characteristics
18–8
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