MC145574 Datasheet, PDF (117/164 Pages) Motorola, Inc – ISDN S/T-Interface Transceiver

Freescale Semiconductor, Inc.
16
TRANSMISSION LINE INTERFACE CIRCUITRY
16.1
INTRODUCTION
The MC145574 is an ISDN S/T transceiver fully compliant with CCITT I.430, ETSI ETS 300012, and
ANSI T1.605. As such, it is designed to interface with a four–wire transmission medium, one pair being
the transmit path, the other pair the receive path. TxP and TxN, a fully–differential output transmit
pair from the MC145574, are designed to interface to the transmit pair of the transmission medium
via auxiliary discrete components and a 1:2.5 turns ratio transformer. RxP and RxN are a high–imped-
ance differential input pair used for coupling the receive line signal through a 1:2.5 turns ratio transform-
er.
16.2
TRANSMIT LINE INTERFACE CIRCUITRY
The TxP and TxN pins on the MC145574 act as a current–limited differential voltage source pair. The
TxP and TxN pair behave as active drivers when creating logical 0 line signals (CCITT I.430, ETSI
ETS 300012, and ANSI T1.605 define the nominal pulse amplitude to be 750 mV, zero to peak, for
a 50 Ω load), and are high–impedance outputs when generating logical 1 signals. The transmit circuitry
within the S/T transceiver is designed to operate with a 1:2.5 turns ratio line interface transformer.
The transmit transformer is similar in design to the receive transformer.
The TxP and TxN pair operate as a 2.8 V current–limited differential voltage source on the device
side (1.12 V on the S/T loop side). As such, two 5% series resistors should be inserted in the line
interface circuit so that the combined resistance of these two resistors and the winding resistance
of the transformer is 145 Ω. The current limit value is set by circuitry within the S/T transceiver and
is approximately 9 mA.
The TxP and TxN transmit pair supplies a current such that a positive potential is created between
the TxP and TxN pins, respectively, when transmitting the F frame bit of each frame. The TxP and
TxN line drive circuit of the MC145574 S/T transceiver is designed such that the device continues
to provide a high–impedance circuit to the transmit pair of the S/T loop when power is removed (i.e.,
when the circuit between VDD and VSS becomes a short circuit). Figure 16–1 illustrates the recom-
mended line interface and protection circuitry for interfacing the MC145574 to the S/T loop.
16.3
RECEIVE LINE INTERFACE CIRCUITRY
The RxP and RxN pins serve as a fully–differential input pair for the line signal from the S/T loop.
The input impedance seen looking into the combination of the MC145574 and the associated receive
line interface circuitry (as shown in Figure 16–2) exceeds the CCITT I.430, ETSI ETS 300012, and
ANSI T1.605 requirements under all conditions. The receive line circuitry within the MC145574 S/T
transceiver is designed to operate with a 1:2.5 turns ratio transformer. The receive transformer is similar
in design to the transmit transformer and a list of suppliers of these transformers are included.
The receive circuitry within the MC145574 automatically adapts to the optimum ternary detection
thresholds for receiving the incoming line signal, regardless of the S/T loop bus configuration. The
minimum ternary detection threshold is 90 mV, referenced to signal ground. This value then sets the
absolute maximum attenuation that can exist, before detection of the incoming signal becomes impos-
sible. The RxP and RxN pair are not sensitive to the polarity of their connection to the line interface
circuitry. Figure 16–2 illustrates the recommended line interface and protection circuitry for interfacing
the MC145574 S/T transceiver to the loop.
MOTOROLA
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16–1