M38207E8FP Datasheet, PDF (63/66 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS
3820 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
SWITCHING CHARACTERISTICS 1 (Low Power Source Voltage Version)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted.)
Symbol
Parameter
twH(SCLK1)
twL(SCLK1)
td(SCLK1–TXD)
tv(SCLK1–TXD)
tr(SCLK1)
tf(SCLK1)
twH(SCLK2)
twL(SCLK2)
td(SCLK2–SOUT2)
tv(SCLK2–SOUT2)
tf(SCLK2)
tr(CMOS)
tf(CMOS)
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time (Note 1)
Serial I/O1 output valid time (Note 1)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time
Serial I/O2 output valid time
Serial I/O2 clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
Min.
tc(SCLK1)/2–30
tc(SCLK1)/2–30
–30
tc(SCLK2)/2–160
tc(SCLK2)/2–160
0
Limits
Unit
Typ.
Max.
ns
ns
140
ns
ns
30
ns
30
ns
ns
ns
0.2!tC(SCLK2) ns
ns
40
ns
10
30
ns
10
30
ns
Notes 1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: XOUT and XCOUT pins are excluded.
SWITCHING CHARACTERISTICS 2 (Low Power Source Voltage Version)
(VCC = 2.2 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted.)
Symbol
Parameter
Limits
Unit
Min.
Typ.
Max.
twH(SCLK1)
twL(SCLK1)
td(SCLK1–TXD)
tv(SCLK1–TXD)
tr(SCLK1)
tf(SCLK1)
twH(SCLK2)
twL(SCLK2)
td(SCLK2–SOUT2)
tv(SCLK2–SOUT2)
tf(SCLK2)
tr(CMOS)
tf(CMOS)
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time (Note 1)
Serial I/O1 output valid time (Note 1)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time
Serial I/O2 output valid time
Serial I/O2 clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
tc(SCLK1)/2–50
tc(SCLK1)/2–50
–30
tc(SCLK2)/2–240
tc(SCLK2)/2–240
0
ns
ns
350 ns
ns
50 ns
50 ns
ns
ns
0.2!tC(SCLK2) ns
ns
50 ns
20
50 ns
20
50 ns
Notes 1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: XOUT and XCOUT pins are excluded.
Measurement output pin
100pF
CMOS output
Fig.41 Circuit for measuring output switching characteristics
Measurement output pin
1kΩ
100pF
N-channel open-drain output (Note)
Note: When bit 4 of the UART
control register (address 001B 16) is “1”.
(N-channel open-drain output mode)
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