M38207E8FP Datasheet, PDF (14/66 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS
3820 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Pin
P00/SEG24–
P07/SEG31
P10/SEG32–
P17/SEG39
P20 – P27
P30/SEG16–
P37/SEG23
P40
P41/ φ
P42/INT0,
P43/INT1
P44/RXD
P45/TXD
P46/SCLK1
P47/SRDY1
P50/SIN2
P51/SOUT2
P52/SCLK2
P53/SRDY2
P54/CNTR0
P55/CNTR1
P56/TOUT
P57/INT2
P60/INT3/RTP0
P61/RTP1
Name
Port P0
Port P1
Port P2
Port P3
Port P4
Port P5
Port P6
Input/Output
Input/output,
individual ports
Input/output,
individual ports
Input/output,
individual bits
Input
Input
Input/output,
individual bits
Input/output,
individual bits
Input/output,
individual bits
I/O Format
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
CMOS compatible
input level
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
Non-Port Function
LCD segment output
LCD segment output
Key input(Key-on
wake up) interrupt
input
LCD segment output
φ clock output
External interrupt input
Serial I/O1 function I/O
Serial I/O2 function I/O
Timer I/O
Timer I/O
Timer output
External interrupt input
External interrupt input
Real time port
function output
Real time port
function output
Related SFRs
PULL register A
Segment output
enable register
PULL register A
Segment output
enable register
PULL register A
Interrupt control
register 2
PULL register A
Segment output
enable register
Diagram No.
(1)
(2)
(3)
(4)
PULL register B
φ output control
(5)
register
PULL register B
Interrupt edge selection
(2)
register
PULL register B
(6)
Serial I/O1 control register
(7)
Serial I/O1 status register
(8)
UART control register
(9)
(10)
PULL register B
(11)
Serial I/O2 control
(12)
register
(13)
PULL register B
(14)
Timer X mode register
PULL register B
(10)
Timer Y mode register
PULL register B
(15)
Timer 123 mode register
PULL register B
Interrupt edge
(2)
selection register
PULL register B
Timer X mode register
Interrupt edge
(16)
selection register
PULL register B
Timer X mode register
P70/XCOUT
CMOS compatible
Sub-clock
(17)
Input/output,
PULL register A
Port P7
input level
generating circuit
individual bits
CPU mode register
P71/XCIN
CMOS 3-state output I/O
(18)
COM0-COM3
SEG0-SEG15
Common
Segment
output
output
LCD common output
LCD segment output
LCD mode register
(19)
(20)
Note : Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction.
When an input level is at an intermediate potential, a current will flow from VCC to VSS through the input-stage gate.
14