M38207E8FP Datasheet, PDF (57/66 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS
3820 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
SWITCHING CHARACTERISTICS 1 (Extended Operating Temperature Version)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted.)
Symbol
Parameter
Limits
Unit
Min.
Typ.
Max.
twH(SCLK1) Serial I/O1 clock output “H” pulse width
tc(SCLK1)/2–30
ns
twL(SCLK1) Serial I/O1 clock output “L” pulse width
tc(SCLK1)/2–30
ns
td(SCLK1–TXD) Serial I/O1 output delay time (Note 1)
140
ns
tv(SCLK1–TXD) Serial I/O1 output valid time (Note 1)
–30
ns
tr(SCLK1)
Serial I/O1 clock output rising time
30
ns
tf(SCLK1)
Serial I/O1 clock output falling time
30
ns
twH(SCLK2) Serial I/O2 clock output “H” pulse width
tc(SCLK2)/2–160
ns
twL(SCLK2) Serial I/O2 clock output “L” pulse width
td(SCLK2–SOUT2) Serial I/O2 output delay time
tc(SCLK2)/2–160
ns
0.2!tC(SCLK2) ns
tv(SCLK2–SOUT2) Serial I/O2 output valid time
0
ns
tf(SCLK2)
Serial I/O2 clock output falling time
40
ns
tr(CMOS)
CMOS output rising time (Note 2)
10
30
ns
tf(CMOS)
CMOS output falling time (Note 2)
10
30
ns
Notes1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: XOUT and XCOUT pins are excluded.
SWITCHING CHARACTERISTICS 2 (Extended Operating Temperature Version)
(VCC = 2.5 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, and VCC = 3.0 to 4.0 V, Ta = –40 to –20 °C, unless otherwise noted.)
Symbol
Parameter
Limits
Unit
Min.
Typ.
Max.
twH(SCLK1) Serial I/O1 clock output “H” pulse width
tc(SCLK1)/2–50
ns
twL(SCLK1) Serial I/O1 clock output “L” pulse width
tc(SCLK1)/2–50
ns
td(SCLK1–TXD) Serial I/O1 output delay time (Note 1)
350 ns
tv(SCLK1–TXD) Serial I/O1 output valid time (Note 1)
–30
ns
tr(SCLK1)
Serial I/O1 clock output rising time
50 ns
tf(SCLK1)
Serial I/O1 clock output falling time
50 ns
twH(SCLK2) Serial I/O2 clock output “H” pulse width
tc(SCLK2)/2–240
ns
twL(SCLK2) Serial I/O2 clock output “L” pulse width
tc(SCLK2)/2–240
ns
td(SCLK2–SOUT2) Serial I/O2 output delay time
0.2!tC(SCLK2) ns
tv(SCLK2–SOUT2) Serial I/O2 output valid time
0
ns
tf(SCLK2)
Serial I/O2 clock output falling time
50 ns
tr(CMOS)
CMOS output rising time (Note 2)
20
50 ns
tf(CMOS)
CMOS output falling time (Note 2)
20
50 ns
Notes1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: XOUT and XCOUT pins are excluded.
Measurement output pin
100pF
CMOS output
Fig.40 Circuit for measuring output switching characteristics
Measurement output pin
1kΩ
100pF
N-channel open-drain output (Note)
Note: When bit 4 of the UART
control register (address 001B 16) is “1”.
(N-channel open-drain output mode)
57