M38207E8FP Datasheet, PDF (56/66 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS
3820 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMING REQUIREMENTS 1 (Extended Operating Temperature Version)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted.)
Symbol
Parameter
tw(RESET)
tc(XIN)
twH(XIN)
twL(XIN)
tc(CNTR)
twH(CNTR)
twL(CNTR)
twH(INT)
twL(INT)
tc(SCLK1)
twH(SCLK1)
twL(SCLK1)
tsu(RXD–SCLK1)
th(SCLK1–RXD)
tc(SCLK2)
twH(SCLK2)
twL(SCLK2)
tsu(SIN2–SCLK2)
th(SCLK2–SIN2)
Reset input “L” pulse width
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
Main clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT3 input “H” pulse width
INT0 to INT3 input “L” pulse width
Serial I/O1 clock input cycle time (Note)
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O1 input set up time
Serial I/O1 input hold time
Serial I/O2 clock input cycle time
Serial I/O2 clock input “H” pulse width
Serial I/O2 clock input “L” pulse width
Serial I/O2 input set up time
Serial I/O2 input hold time
Limits
Unit
Min. Typ. Max.
2
µs
125
ns
45
ns
40
ns
250
ns
105
ns
105
ns
80
ns
80
ns
800
ns
370
ns
370
ns
220
ns
100
ns
1000
ns
400
ns
400
ns
200
ns
200
ns
Note: When f(XIN) = 8 MHz and bit 6 of address 001A16 is “1” (clock synchronous).
Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is “0” (UART).
TIMING REQUIREMENTS 2 (Extended Operating Temperature Version)
(VCC = 2.5 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, and VCC = 3.0 to 4.0 V, VSS = 0 V, Ta = –40 to –20 °C, unless otherwise noted.)
Symbol
Parameter
Limits
Unit
Min. Typ. Max.
tw(RESET) Reset input “L” pulse width
2
µs
tc(XIN)
Main clock input cycle time (XIN input)
125
ns
twH(XIN)
Main clock input “H” pulse width
45
ns
twL(XIN)
Main clock input “L” pulse width
40
ns
tc(CNTR)
CNTR0, CNTR1 input cycle time
500/
(VCC–2)
ns
twH(CNTR) CNTR0, CNTR1 input “H” pulse width
250/
ns
(VCC–2)–20
twL(CNTR) CNTR0, CNTR1 input “L” pulse width
250/
ns
(VCC–2)–20
twH(INT)
INT0 to INT3 input “H” pulse width
230
ns
twL(INT)
INT0 to INT3 input “L” pulse width
230
ns
tc(SCLK1)
Serial I/O1 clock input cycle time (Note)
2000
ns
twH(SCLK1) Serial I/O1 clock input “H” pulse width (Note)
950
ns
twL(SCLK1) Serial I/O1 clock input “L” pulse width (Note)
950
ns
tsu(RXD–SCLK1) Serial I/O1 input set up time
400
ns
th(SCLK1–RXD) Serial I/O1 input hold time
200
ns
tc(SCLK2)
Serial I/O2 clock input cycle time
2000
ns
twH(SCLK2) Serial I/O2 clock input “H” pulse width
950
ns
twL(SCLK2) Serial I/O2 clock input “L” pulse width
950
ns
tsu(SIN2–SCLK2) Serial I/O2 input set up time
400
ns
th(SCLK2–SIN2) Serial I/O2 input hold time
300
ns
Note: When f(XIN) = 2 MHz and bit 6 of address 001A16 is “1” (clock synchronous).
Divide this value by four when f(XIN) = 2 MHz and bit 6 of address 001A16 is “0” (UART).
56