M5M4V16169DTP Datasheet, PDF (62/64 Pages) Mitsubishi Electric Semiconductor – 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM

MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
Set Command Register(2)
Address Input
Command
Ad11 Ad10 Ad9
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
Ad8 Ad7
L
L
L
H
H
L
H
H
Ad6
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Ad5 Ad4
LL
LH
HL
HH
Ad3 Ad2 Ad1 Ad0
L
L
No operation
L
H
Set All WB1 Xfer Masks
L
Default
L
L
L
Output ModeTransparent
L
H
L
Output Mode Latched
H
L
L
Output Mode Registered
L
Latency 1
L
Latency 2
L
Latency 3
L
Latency 4
L
Default
L
BL=1
L
BL=2
L
BL=4
L
BL=8
L
Sequential
L
Interleave
L
Default
L
Default
K
CMd#
CS#
RAS#
CAS#
* Latency is the number of clock
cycles required to transfer new
data from the DRAM to the Read
Buffer . Therefore, it can be
adjusted to the clock frequency of
the system.
(Latency) x (tK) should meet tCBF
min. timing requirement.
DTD#
Ad0~11
Command
SCR
Inhibit new read or write function during these 4 clocks.
MITSUBISHI ELECTRIC
62
(REV 1.0) Jul. 1998