M5M4V16169DTP Datasheet, PDF (1/64 Pages) Mitsubishi Electric Semiconductor – 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM

MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
Preliminary
This document is a preliminary Target Spec. and some of the contents are subject to change without notice.
DESCRIPTION
PINCONFIGURATION
(TOP VIEW)
1. ^{The M5M4V16169DTP/RT is a 16M-bit Cached DRAM which integrates input}
registers, a 1,048,576-word by 16-bit dynamic memory array and a 1024- word
by 16-bit static RAM array as a Cache memory (block size 8x16) onto a single
monolithic circuit. The block data transfer between the DRAM and the data
transfer buffers (RB1/RB2/WB1/WB2) is performed in one instruction cycle, a
fundamental advantage over a conventional DRAM/SRAM cache.
The RAM is fabricated with a high performance CMOS process, and is ideal for
2. ^{large-capacity memory systems where high speed, low power dissipation, and}
low cost are essential. The use of quadruple-layer polysilicon process combined
Vcc 1
DQCl 2
DQCu 3
CC1# 4
CC0# 5
WE# 6
CS# 7
CMd# 8
CMs# 9
K 10
DQ0 11
Vss 12
DQ1 13
DQ2 14
400 mil
70 Vss
69 Ad9
68 Ad8
67 Ad7
66 Ad11
65 Ad10
64 As9
63 As8
62 As7
61 As6
60 DQ15
59 Vss
58 DQ14
57 DQ13
with silicide and double layer aluminum wiring technology, a single-transistor
dynamic storage stacked capacitor cell, and a six-transistor static storage cache
cell provide high circuit density at reduced costs.
VddQ 15
DQ3 16
Vss 17
DQ4 19
70Pin
TSOP
Type II
56 VccQ
55 DQ12
54 Vcc
52 DQ11
FEATURES
VccQ 20
DQ5 21
DQ6 22
Vss 23
0.65mm
Lead
Pitch
51 VccQ
50 DQ10
49 DQ9
48 Vss
DQ7 24
47 DQ8
Type name
M5M4V16169TP/RT-7
M5M4V16169TP/RT-8
M5M4V16169TP/RT-10
SRAM
Access/cycle
5.6ns/7ns
6.4ns/8ns
8.0ns/10ns
DRAM
Access/cycle
49ns/70ns
56ns/80ns
60ns/90ns
Power
Dissipation (Typ)
DRAM: 530
SRAM: 860
DRAM: 500
SRAM: 800
DRAM: 430
SRAM: 660
MCL 25
As0 26
As1 27
As2 28
RAS# 29
CAS# 30
DTD# 31
Ad0 32
Ad1 33
Ad2 34
Vcc 35
46 MCH
45 G#
44 As5
43 As4
42 As3
41 Ad6
40 Ad5
39 Ad4
38 Ad3
37 ADF#
36 Vss
M5M4V16169TP/RT-15
8.0ns/15ns
75ns/120ns
DRAM: 330
SRAM: 420
# 70-pin,400-mil TSOP (type II ) with 0.65mm
lead pitch and 23.49mm package length.
# Multiplexed DRAM address inputs for reduced pin
count and higher system densities.
# Selectable output operation (transparent / latched /
registered) using set command register cycle.
# Single 3.3V +/- 0.3V Power Supply.
(3.3V +/- 0.15V for -7 part)
# 2048 refresh cycles every 64ms (Ad0->Ad10).
# Programmable burst length (1,2,4,8) and burst
sequence (sequential,interleave) with no latency.
# Synchronous design for precise control with
an external clock (K).
# Output retention by advanced mask clock (CMs#).
# All inputs/outputs low capacitance and LVTTL
compatible.
# Separate DRAM and SRAM address inputs
for fast SRAM access.
# Page Mode capability.
# Auto Refresh capability.
# Self Refresh capability.
K
CS#
CMd#
RAS#
: Master Clock
: Chip Select
: DRAM Clock Mask
: Row Addr. Strobe
CAS#
: Column Addr. Strobe
DTD#
: Data Transfer Direction
Ad
: DRAM Address
CMs#
: SRAM Clock Mask
CC0#,CC1# ^{: Control Clocks}
WE#
: Write Enable
DQC(u/l) ^{: I/O Byte Control}
As
: SRAM Address
G#
DQ
Vcc
VccQ
Vss
ADF#
: Output Enable
: Data I/O
: Power Supply
: DQ Power Supply
: Ground
:Address Fetch clock
This pin can be None-Connect.
MCL
MCH
:Must Connect Low
:Must Connect High
Vss
Ad9
Ad8
Ad7
Ad11
Ad10
As9
As8
As7
As6
DQ15
Vss
DQ14
DQ13
VccQ
DQ12
Vcc
DQ11
VccQ
DQ10
DQ9
Vss
DQ8
MCH
G#
As5
As4
As3
Ad6
Ad5
Ad4
Ad3
ADF#
Vss
Package code:70P3S-L
70
1
69
2
68
3
67
4
66
5
65
6
64
7
63
8
62
9
61
10
60
11
59
12
58
13
57
400 mil
14
56
70Pin
15
55
TSOP
16
54
Type II
17
52
19
51
0.65mm
20
50
Lead
21
49
Pitch
22
48
23
47
24
46
25
45
26
44
27
43
28
42
29
41
30
40
31
39
32
38
33
37
34
36
35
Vcc
DQCl
DQCu
CC1#
CC0#
WE#
CS#
CMd#
CMs#
K
DQ0
Vss
DQ1
DQ2
VccQ
DQ3
Vss
DQ4
VccQ
DQ5
DQ6
Vss
DQ7
MCL
As0
As1
As2
RAS#
CAS#
DTD#
Ad0
Ad1
Ad2
Vcc
Package code:70P3S-M
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
1