M5M4V16169DTP Datasheet, PDF (50/64 Pages) Mitsubishi Electric Semiconductor – 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM

MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
Page-Mode DRAM Read Transfer Latency set=4
1 2 3 4 5 6 7 8 9 10 11 12 13 14
K
CMd#
CS#
RAS#
CAS#
tRCD
tRASP
tPC
tRSH
DTD#
Ad0-2
Ad3-11
RB
RB
DRAM
SRAM
DQ0-15
Row
Ad0-Ad2=Low
Row
**C1
**C2
**C3
tCBF
tCBF
tCBF
Old Data
C1
C2
C3
Latency x tK
Latency x tK
Old Data
C1
C3
DPD ACT DNOP DRT DNOP DNOP DNOP DRT DNOP DRT DNOP DNOP PCG
BR BR BR BR BR BR BR BR BR BR BR BR BR BR
Old Old Old Old Old Old Old Q1 Q1 Q1 Q1 Q1 Q1 Q3
If next DRT happens within the latency,
new data does not transferred to RB.
However this operation is not guaranteed.
SRAM operation can be freely performed.
MITSUBISHI ELECTRIC
** Ad3-Ad7 are column block addresses (Ad8~Ad11=Low).
(REV 1.0) Jul. 1998
50