M5M4V16169DTP Datasheet, PDF (49/64 Pages) Mitsubishi Electric Semiconductor – 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM

MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
Page-Mode DRAM Read Transfer Latency set=3
1 2 3 4 5 6 7 8 9 10 11 12 13 14
K
CMd#
CS#
RAS#
CAS#
tRCD
tRASP
tPC
tPC
tRSH
DTD#
Ad0-2
Ad3-11
RB1
RB2
DRAM
SRAM
Row
Ad0-Ad2=Low
Row
Old Data
Old Data
**C1
**C2
**C3 **C4
tCBF
C1
Latency x tK
tCBF
C2
Latency x tK
C1
tCBF tCBF
C3
C4
Latency x tK
C2
C4
DPD ACT DNOP DRT DNOP DNOP DRT DNOP DNOP DRT DRT DNOP PCG
BR BR BR BR BR BR BR BR BR BR BR BR BR BR
DQ0-15
Old Old Old Old Old Old Q1 Q1 Q1 Q2 Q2 Q2 Q2 Q4
If next DRT happens within the latency,
new data does not transferred to RB.
However this operation is not guaranteed.
SRAM operation can be freely performed.
MITSUBISHI ELECTRIC
** Ad3-Ad7 are column block addresses (Ad8~Ad11=Low).
(REV 1.0) Jul. 1998
49