M38197MA Datasheet, PDF (24/60 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0 _{Serial I/O1 control register}
b7
b0 _{Serial I/O2 control register}
(SIO1CON(SC1) : address 001916)
(SIO2CON(SC2) : address 001D16)
Internal synchronous clock selection bits
Internal synchronous clock selection bits
b2 b1 b0
b2 b1 b0
0 0 0 : f(XIN)/8 or f(XCIN)/8
0 0 1 : f(XIN)/16 or f(XCIN)/16
0 1 0 : f(XIN)/32 or f(XCIN)/32
0 1 1 : f(XIN)/64 or f(XCIN)/64
1 1 0 : f(XIN)/128 or f(XCIN)/128
1 1 1 : f(XIN)/256 or f(XCIN)/256
Serial I/O1 port selection bit (P65, P66, and P67 ^V)
0 : I/O port
1 : SOUT1,SCLK11,and SCLK12 ^V output pins
SRDY1 output selection bit (P67)
0 : I/O port
1 : SRDY1/CS ^V output pin (Note)
Transfer direction selection bit
0 0 0 : f(XIN)/8 or f(XCIN)/8
0 0 1 : f(XIN)/16 or f(XCIN)/16
0 1 0 : f(XIN)/32 or f(XCIN)/32
0 1 1 : f(XIN)/64 or f(XCIN)/64
1 1 0 : f(XIN)/128 or f(XCIN)/128
1 1 1 : f(XIN)/256 or f(XCIN)/256
Serial I/O2 port selection bit (P51, and P52)
0 : I/O port
1 : SOUT2 and SCLK2 output pins
SRDY2 output selection bit (P53)
0 : I/O port
1 : SRDY2 output pin
Transfer direction selection bit
0 : LSB first
0 : LSB first
1 : MSB first
1 : MSB first
Synchronous clock selection bit
Synchronous clock selection bit
0 : External clock
0 : External clock
1 : Internal clock
1 : Internal clock
P65/SOUT1 P-channel output disable bit
0 : CMOS output (in output mode)
P51/SOUT2 P-channel output disable bit
0 : CMOS output (in output mode)
1 : N-channel open-drain output
(in output mode)
1 : N-channel open-drain output
(in output mode)
b7
b0 _{Serial I/O3 control register}
(SIO3CON(SC3) : address 001E16)
Internal synchronous clock selection bits
b2 b1 b0
0 0 0 : f(XIN)/8 or f(XCIN)/8
0 0 1 : f(XIN)/16 or f(XCIN)/16
0 1 0 : f(XIN)/32 or f(XCIN)/32
0 1 1 : f(XIN)/64 or f(XCIN)/64
1 1 0 : f(XIN)/128 or f(XCIN)/128
1 1 1 : f(XIN)/256 or f(XCIN)/256
Serial I/O3 port selection bit (P55 and P56)
0 : I/O port
1 : SOUT3 and SCLK3 output pins
SRDY3 output selection bit (P57)
0 : I/O port
1 : SRDY3 and SCLK3 output pins
Transfer direction selection bit
0 : LSB first
1 : MSB first
Synchronous clock selection bit
0 : External clock
1 : Internal clock
P55/SOUT3 P-channel output disable bit
0 : CMOS output (in output mode)
1 : N-channel open-drain output
(in output mode)
V _{: Valid only in serial I/O automatic transfer mode.}
Note: When the external clock is selected in the serial I/O1 automatic transfer mode, the SRDY1 signal pin becomes the CS signal input pin.
Fig. GA-2 Structure of serial I/O control registers
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