M38197MA Datasheet, PDF (16/60 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
INTERRUPTS
Interrupts occur by 20 sources: 5 external, 14 internal, and 1 soft-
ware.
Interrupt Control
Each interrupt is controlled by an interrupt request bit, an interrupt
enable bit, and the interrupt disable flag except for the software in-
terrupt set by the BRK instruction. An interrupt occurs if the
corresponding interrupt request and enable bits are “1” and the in-
terrupt disable flag is “0”.
Interrupt enable bits can be set or cleared by software.
Interrupt request bits can be cleared by software, but cannot be
set by software.
The BRK instruction cannot be disabled with any flag or bit.
The I (interrupt disable) flag disables all interrupts except the BRK
instruction interrupt.
Interrupt Operation
When an interrupt is received, the contents of the program counter
and processor status register are automatically stored into the
stack. The interrupt disable flag is set to inhibit other interrupts
from interfering. The corresponding interrupt request bit is cleared
and the interrupt jump destination address is read from the vector
table into the program counter.
Notes on Use
When the active edge of an external interrupt (INT0 to INT4) is
changed or when switching interrupt sources in the same vector
address, the corresponding interrupt request bit may also be set.
Therefore, please take following sequence;
(1) Disable the external interrupt which is selected.
(2) Change the active edge.
(3) Clear the interrupt request bit which is selected to “0”.
(4) Enable the external interrupt which is selected.
Table 1. Interrupt vector addresses and priority
Interrupt Source
Reset (Note 2)
INT0
INT1/ZCR
INT2
Remote control/
counter overflow
Serial I/O1
Serial I/O
automatic transfer
Serial I/O2
Priority
1
2
3
4
5
6
Vector Addresses (Note 1)
High
Low
FFFD16
FFFC16
FFFB16
FFFA16
FFF916
FFF816
FFF716
FFF616
FFF516
FFF316
FFF416
FFF216
Interrupt Request
Generating Conditions
At reset
At detection of either rising or
falling edge of INT0 input
At detection of either rising or
falling edge of INT1/ZCR input
At detection of either rising or
falling edge of INT2 input
At 8-bit counter overflow
At completion of data transfer
At completion of the last data
transfer
At completion of data transfer
Serial I/O3
Timer 1
Timer 2
Timer 3
Timer 4
Timer 5
Timer 6
INT3
7
FFF116
FFF016
At completion of data transfer
8
FFEF16
FFEE16
At timer 1 underflow
9
FFED16
FFEC16
At timer 2 underflow
10
FFEB16
FFEA16
At timer 3 underflow
11
FFE916
FFE816
At timer 4 underflow
12
FFE716
FFE616
At timer 5 underflow
13
FFE516
FFE416
At timer 6 underflow
At detection of either rising or
14
FFE316
FFE216
falling edge of INT3 input
INT4
A-D conversion
FLD blanking
FLD digit
At detection of either rising or
15
FFE116
FFE016
falling edge of INT4 input
At completion of A-D conver-
sion
At falling edge of the last digit
immediately before blanking
16
FFDF16
FFDE16
period starts
At rising edge of each digit
BRK instruction
17
FFDD16
FFDC16
At BRK instruction execution
Notes 1 : Vector addresses contain interrupt jump destination addresses.
2 : Reset function in the same way as an interrupt with the highest priority.
Remarks
Non-maskable
External interrupt (active edge
selectable)
External interrupt (active edge
selectable)
External interrupt (active edge
selectable)
Valid when interrupt interval
determination is operating
Valid when serial I/O ordinary
mode is selected
Valid when serial I/O automatic
transfer mode is selected
Valid when serial I/O2 is se-
lected
Valid when serial I/O3 is se-
lected
STP release timer underflow
External interrupt (active edge
selectable)
Valid when INT4 interrupt is
selected
External interrupt (active
edge selectable)
Valid when A-D conversion in-
terrupt is selected
Valid when FLD blanking in-
terrupt is selected
Valid when FLD digit interrupt
is selected
Non-maskable software inter-
rupt
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