M38197MA Datasheet, PDF (10/60 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
I/O PORTS
Direction Registers
The 3819 group has 54 programmable I/O pins arranged in 8 I/O
ports (ports P24–P27, P41–P44, P46, P47, P5–P8, PA, and PB).
The I/O ports have direction registers which determine the input/
output direction of each individual pin. Each bit in a direction reg-
ister corresponds to one pin, each pin can be set to be input or
output.
When “0” is written to the bit corresponding to a pin, that pin be-
comes an input pin. When “1” is written to that bit, that pin
becomes an output pin.
If data is read from a pin which is set for output, the value of the
port latch is read, not the value of the pin itself. A pin which is set
for input the value of the pin itself is read because the pin is in
floating state. If a pin set for input is written to, only the port latch
is written to and the pin remains floating.
High-Breakdown-Voltage Output Ports
The 3819 group microprocessors have 7 ports with high-break-
down-voltage pins (ports P0, P1, P20–P23, P3, P8, P9, PA). The
high-breakdown-voltage ports have P-channel open-drain output
with VCC –40 V of breakdown voltage.
Each pin in ports P0, P1, P20–P23, P3, and P9 has an internal
pull-down resistor connected to VEE. Ports P8 and PA have no in-
ternal pull-down resistors, so that connect an external resistor to
each port. At reset, the P-channel output transistor of each port
latch is turned off, so it becomes VEE level (“L”) by the pull-down
resistor.
Writing “1” (weak drivability) to bit 7 of the FLDC mode register 1
(address 003616) shows the rising transition of the output transis-
tors for reducing transient noise. At reset, bit 7 of the FLDC mode
register 1 is set to “0” (strong drivability).
Pin
P00/SEG32/
DIG0–
P07/SEG39/
DIG7
P10/SEG40/
DIG8–
P17/DIG15
P20/DIG16–
P23/DIG19
P24–P27
P30/SEG24–
P37/SEG31
P40/INT0
P45/INT1/
ZCR
P42/INT2–
P44/INT4
P41
P46/T1OUT,
P47/T3OUT
Name
Port P0
Port P1
Port P2
Port P3
Port P4
Input/Output
Output
Output
Output
Input/output,
individual bits
Output
Input
Input/output,
individual bits
I/O Format
High-breakdown-
voltage P-channel
open-drain output
with pull-down
resistor
High-breakdown-
voltage P-channel
open-drain output
with pull-down
resistor
High-breakdown-
voltage P-channel
open-drain output
with pull-down
resistor
TTL level input
CMOS 3-state output
High-breakdown-
voltage P-channel
open-drain output
with pull-down
resistor
CMOS compatible
input level
CMOS compatible
input level
CMOS 3-state output
Non-Port Function
FLD automatic dis-
play function
Related SFRS
Diagram
No.
FLDC mode register 1
FLDC mode register 2
Port P0
(1)
segment/digit
switch register
FLD automatic dis- ^{FLDC mode register 1} (1)
play function
FLDC mode register 2 ₍₂₎
FLDC mode register 1
FLD automatic dis- _{FLDC mode register 2}
play function
(3)
Port P2 digit/port
switch register
(4)
FLD automatic dis- FLDC mode register 1
play function
(5)
FLDC mode register 2
External interrupt _{Interrupt edge}
input
selection register
(6)
Zero cross detec- _{Zero cross detection}
tion circuit input _{control register}
(P45)
(7)
Timer output
(4)
Timer 12 mode register
(8)
Timer 34 mode register
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