MT90500 Datasheet, PDF (88/159 Pages) Mitel Networks Corporation – Multi-Channel ATM AAL1 SAR

MT90500
Address: 2002 (Hex)
Label: TXSS
Reset Value: 0000 (Hex)
Label
SCHEDULE
Bit
Position
6
Reserved
14:7
TXSERV
15
Table 18 - TX_SAR Status Register
Type
Description
R/O/L
R/O
R/W
Scheduler Error. The TX_SAR has too heavy a work load (e.g. too many events per
scheduler frame; uneven distribution of events throughout the scheduler). To recover, the
schedulers must be stopped and re-balanced. The TX Control Structures must also be re-
initialized. Writing a ‘1’ over this bit clears it. Fatal error.
Reserved. Always read as “000_0000_0”.
TX Service. This bit is set if bit<5> or bit<6> is set.
Table 19 - TX_SAR Scheduler Base Register
Address: Scheduler A: 2010 (Hex); Scheduler B: 2020 (Hex); Scheduler C: 2030 (Hex)
Label: TESBAA; TESBAB; TESBAC
Reset Value: 0000 (Hex)
Label
Bit Position Type
Description
SBASE
11:0
R/W Scheduler Base Address. This register contains bits<20:9> of the base address of an
event scheduler. Bits<8:0> are always 000h. This register must not be changed when the
scheduler is enabled.
ENTRY
15:12
R/W Entries per Frame. This register contains the number of entries in one frame on the
scheduler. “0000” = 8 entries; “0001” = 16 entries; “0010” = 32 entries; all other values are
reserved. This register must not be changed when the scheduler is enabled.
Note: All scheduler entries must be read from external SSRAM to check if they are active or inactive. Better memory-bandwidth efficiency is
achieved with fewer entries-per-frame and events distributed throughout the frames of the scheduler, as opposed to having bursts of events
and many inactive entries.
Table 20 - TX_SAR Frame End Register
Address: Scheduler A: 2012 (Hex); Scheduler B: 2022 (Hex); Scheduler C: 2032 (Hex)
Label: TESFEA; TESFEB; TESFEC
Reset Value: 0000 (Hex)
Label
SHTEND
LNGEND
Bit Position
7:0
15:8
Type
R/W
R/W
Description
Short End Frame. This register indicates the number of the last frame when the scheduler
is executing a short turn. This register must not be changed when the scheduler is
enabled.
Long End Frame. This register indicates the number of the last frame when the scheduler
is executing a long turn. This register must not be changed when the scheduler is enabled.
Table 21 - TX_SAR End Ratio Register
Address: Scheduler A: 2014 (Hex); Scheduler B: 2024 (Hex); Scheduler C: 2034 (Hex)
Label: TESERA; TESERB; TESERC
Reset Value: 0000 (Hex)
Label
RATIO
Bit Position
2:0
Type
R/W
Description
Long/Short Ratio. This register indicates how many long turns a scheduler must execute
for one short turn. In other words, the value in this register is the non-P: P-cell ratio. For
pointerless cells, the value must be “000”. For structured cells, the value can be “001”
(1:1), “011” (3:1), or “111” (7:1). This register must not be changed when the scheduler is
enabled.
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