MT90500 Datasheet, PDF (38/159 Pages) Mitel Networks Corporation – Multi-Channel ATM AAL1 SAR

MT90500
4.2 External Memory Controller
The external memory controller block of the MT90500 resides between the internal blocks and the external
memory. It receives memory access requests from the internal blocks (TDM Interface, TX_SAR, RX_SAR,
UTOPIA, and Microprocessor modules) and services them by reading data from, or writing data to, the external
memory. The MT90500 pins connecting to the external memory consist of: 18 address bits (MEM_ADD[17:0]),
4 memory bank/chip selection bits (MEM_CS[1:0][H/L]), 32 data bits (MEM_DAT[31:0]), 4 parity bits
(MEM_PAR[3:0]) used as TDM Read Underrun flags, 4 write enable bits (MEM_WR[3:0]), a memory output
enable bit (MEM_OE), and a memory clock (MEMCLK). The external memory controller block ensures the
proper timing of all memory signals and the flow control of the external memory’s data bus. The external
memory controller block also converts a 21-bit internal byte-oriented address to a memory bank selection and
a physical address. (The 2 LSBs select one byte within the 4-byte/double-word wide data bus, up to 18 bits
select a particular double-word address, and the MSB selects one of two possible memory banks.)
The external memory controller block implements memory accesses to an external 36-bit Synchronous Static
Random Access Memory (SSRAM or Sync SRAM). It supports one or two banks of external memory, each
bank having a total capacity ranging from 32K x 36 bits to 256K x 36 bits. Thus the MT90500 can operate with
external memory ranging from 128 Kbytes to 2,048 Kbytes.
The external memory controller can interface with several different types of Sync SRAM, but they must support
synchronous bus enabling. Synchronous bus enabling means that the Sync SRAM chip must ONLY enable its
data output buffers one cycle after a read (two cycles for pipelined SSRAM), regardless of the state of the
asynchronous output enable pin (MEM_OE). A read is indicated by MEM_WR[3:0] all HIGH, and the
appropriate MEM_CS[1:0][H/L] asserted. The SSRAM must also support single cycle writes (“early” write, or
ADSC type writes). The SSRAM can be a registered-input type (“Synchronous,” “Synchronous Flow-Through,”
or “Synchronous Burst”) or a registered-input/registered-output type (“Synchronous Pipelined”). Although the
MT90500 uses the synchronous access feature of these memories, it does not use the burst access features of
these memories, since most MT90500 memory accesses are random rather than sequential.
Although write accesses to Synchronous SRAM and to Synchronous Pipelined SRAM are identical, there is a
difference in the number of clock cycles before data is returned on the data bus during read accesses. The
MT90500 supports memories with 1, 2 and 3 stages of pipelining (see Figure 8). Both 18-bit and 36-bit data
bus memories are supported, but in the first case, two chips must be used in parallel to form a 36-bit data bus.
Also, two 36-bit wide memory banks can be joined to double the memory’s capacity (see Figure 9). Table 9 lists
most of the possible memory size combinations. (Note: 16-bit and 32-bit memories can be used, but in that
case the TDM Read Underrun indication will not be available.) All chips used must be of the same type.
CLOCK
ADDRESS
DATA
ADDRESS1
ADDRESS2
DATA1
DATA1
DATA1
Note: The number of clock cycles between an address (ADDRESS1) and its
read data (DATA1) is set according to READLEN in the Memory
Configuration Register at address 0040h. Values greater than 3 are reserved.
Figure 8 - Memory Read Pipeline Length
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