MT90500 Datasheet, PDF (77/159 Pages) Mitel Networks Corporation – Multi-Channel ATM AAL1 SAR

MT90500
4.7 Microprocessor Interface
4.7.1 General
This interface allows an external control device (microprocessor) to configure and confirm the status of the
MT90500 via access to internal control and status registers and access to the external device memories. It
supports a variety of software maskable interrupt services.
The CPU interface allows external microprocessors to program the MT90500 and its external memory. The
interface supports word (16-bit) data accesses only. The AEM pin determines if the access is to internal
registers (‘0’), or to external memory (‘1’).
The CPU module features internal registers that are used to control and monitor the operation of the MT90500.
See Main Control Register (0000h) and Main Status Register (0002h) in Section 5.2.
Detailed timing diagrams for the microprocessor interface are shown in Section 6.2.3, “CPU Interface -
Accessing Registers and External Memory”.
4.7.2 A Programming Example - How to Set Up a VC
The basic sequence for initializing a connection at the MT90500 can be summarized in 5 functional steps.
In outlining the basic steps, we consider the need to allocate an ATM Virtual Circuit to one or more 64 kbps
channels present at the ST-BUS interface (ST[15:0]). In this particular scenario, we focus on a channel to be
received from the ST-BUS interface and sent out at the ATM interface (i.e. the transmit process). A similar
procedure (albeit in the reverse order) will have to be repeated for the case whereby an ATM VC is received
and transferred to the associated 64 kbps channel at the ST-BUS interface (i.e. the receive process).
1 - The CPU identifies which 64 kbps time slot(s) or N x 64 kbps grouped channel(s) must be selected
on the ST-BUS backplane. The identification of the selected channels is done via a command from the
driver managing the device.
2 - The CPU identifies which of the Transmit Circular Buffers are available to receive the 64 kbps time
slots from the ST-BUS interface. The number of circular buffers available will depend on the number of
time slots and the data rate selected at the ST-BUS backplane interface (256 time slots @ 2.048 Mbps,
512 time slots @ 4.096 Mbps or 1024 time slots @ 8.192 Mbps).
3 - Once the selection of the circular buffers is made, the CPU maps the time slots to be serviced and
therefore to be transferred to the external circular buffers. This is performed via programmable pointers
in the Transmit Circular Buffer Control Structure, located in external memory.
4 - The CPU starts filling the Transmit Control Structure(s). This information is programmed in external
memory and identifies (in summary) the ATM cell header bytes, the circular buffer address(es) from
which the device will take the time slots and assemble cells, and whether or not this is a partially-filled
cell.
5 - Once the ATM cell structure for a particular VC is complete, the CPU can program the scheduler,
which basically tells the MT90500 how many and which tasks must be executed every 125 µs.
If multiple ATM Virtual Circuits have to be opened simultaneously, the CPU can execute items 1 to 4 taking into
consideration all the TDM channels being treated. However, item 5 can be optimized to provide some fairness
in the general TX_SAR engine so that the device can perform up to 1024 specific ATM VC cell assembly
functions using minimal memory and processing time requirements. The details of that operation, as well as
specific VC setup examples, are provided in the MT90500 Programmers’ Manual.
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