MT90500 Datasheet, PDF (145/159 Pages) Mitel Networks Corporation – Multi-Channel ATM AAL1 SAR

MT90500
7.3 TDM Clock Recovery Applications
7.3.1 General
By the nature of its function - carrying isochronous traffic over Asynchronous Transfer Mode networks - the
MT90500 is used in applications which require some level of synchronization of the TDM clocks at the two ends
of the link. Further, these applications often require the transfer, or recovery, of the isochronous TDM timing
using the ATM link. There are several approaches to TDM clock synchronization, both standardized and not-
standardized. These clock synchronization methods include:
• plesiochronous - where the ATM link is not required to carry timing information, as the timing at both
ends is obtained from plesiochronous trunks (perhaps separate public TDM network trunks);
• synchronous, or physical layer - where the timing for both ends is derived from the ATM physical link
clock;
• adaptive - where timing is carried end-to-end via the ATM cell stream;
• SRTS - a standardized method where timing is carried via time stamps in the ATM cell stream,
against the ATM physical link clock;
• freerun - where no clock synchronization is used at all.
The choice of clock synchronization method is dependent upon the application. Most standards documents
which deal with this issue specify that the recovered clock should be synchronized to the most accurate clock
available. The ITU-T Recommendation I.363.1 provides some guidance on these issues; see the “Convergence
Sublayer” section, especially “Source clock frequency recovery method,” and Appendix II. The reader is also
directed to the Mitel Semiconductor Application Note in this topic.
7.3.2 SRTS Clock Recovery Considerations
The SRTS (Synchronous Residual Time Stamp) method uses the CSI bit in the AAL1 byte to carry time stamp
information over the ATM data link. Figure 70 shows a generic SRTS application. At the source end, the RTS
(Residual Time Stamp) is generated by comparing a divided-down ATM network clock f_nx to a TDM service
clock f_s. (The TDM service clock f_s is generated internally to the MT90500.) The RTS is transmitted, once every
8-cell sequence, to the far end. Using the common ATM network clock (synchronous f_nx) and the RTS, the far
end can recover the TDM clock. Implementation details are given in Section 4.6.2, “SRTS Clock Recovery
Description,” on page 72.
Note that in order to implement SRTS clock recovery properly, both the timing source and the far end node
must share a common reference ATM network clock. If a different ATM network clock is present at either end,
the recovered TDM clocks will be inaccurate in proportion to the difference in the two ATM network clocks.
Where the ATM network clocks are not synchronous, or where it is not known if the ATM network clocks are
synchronous, adaptive clock recovery can often be used.
Since the MT90500 is a backplane device, it must work with a fixed clock rate of 2.048 MHz, 4.096 MHz or
8.192 MHz, rather than the Service Clock rate carried by the SRTS link, as given in ITU-T Recommendation
I.363.1. The SRTS Transmit Divider (see Figure 33) constructs the Service Clock from the TDM bus clocks.
Due to internal sampling in the MT90500, there are certain values of TDM-channels-per-VC that are not
recommended for the VC carrying the SRTS information. These are listed in Table 101. If a clock slower than
60 MHz is being used for MCLK, the designer should note that FNXI must be less than one-third the rate of
MCLK.
Table 101 - Recommended TDM Channel Numbers for SRTS VCs
Recommended
Reduced Accuracy
Not Recommended
Number of TDM Channels Carried by the SRTS VC
1, 2, 3, 4, 5, 6, 8, 10, 12, 15, 16, 20, 24, 25, 30, 32, 40, 45, 48, 50, 60, 64,
75, 80, 90, 96
7, 9, 11, 13, 14, 17, 18, 21, 23, 28, 36, 51, 85
19, 22, 26, 27, 29, 31, 33, 34, 35, 37, 38, 39, 41, 42, 43, 44, 46, 47, 49, 52,
53, 54, 55, 56, 57, 58, 59, 61, 62, 63, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74,
76, 77, 78, 79, 81, 82, 83, 84, 86, 87, 88, 89, 91, 92, 93, 94, 95
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