PDSP16256 Datasheet, PDF (7/28 Pages) Mitel Networks Corporation – Programmable FIR Filter

PDSP16256
DATA
OUT
ACCUMULATE
EXPANSION
IN
DATA
DELAY LINE
DATA
DELAY LINE
DATA
DELAY LINE
DATA
DELAY LINE
DATA
IN
COEFF
RAM
ADDER
Z²¹
COEFF
RAM
ADDER
Z²¹
COEFF
RAM
ADDER
Z²¹
COEFF
RAM
ADDER
RESULT
OUT
Z²¹
Figure. 5 Filter network diagram
Single Filter Options
When operating as a single filter the device accepts data
on the 16-bit DA bus at the selected sample rate, see
Figs. 5 and 6. Results are presented on the 32-bit F bus,
which may be tristated using the OEN input. Signal OEN is
registered onto the device and does not therefore take
effect until the first SCLK rising edge. Devices may be
cascaded this allows filters with more taps than available
from a single device. To accomplish this two further
buses are utilised. The DB bus presents the input data to
the next device in cascade after the appropriate delay,
while, partial results are accepted on the X bus.
Single filter mode is selected by setting control register bit
15 to a one. The required filter length is then selected
using control register bits 14 and 13 as summarised in
Table 3. The options define the number of times each
multiplier accumulator is used per sample clock period.
This can be once, twice, four times, or eight times.
In addition a normal/decimate bit (CR12) allows the filter
length to be doubled at any sample rate. This is possible
when the filter coefficients are selected to produce a low
pass filter, since the filtered output would then not contain
CR
Input
14 13 12 Rate
0 0 0 SCLK
0 0 1 SCLK
0 1 0 SCLK/2
0 1 1 SCLK/2
1 0 0 SCLK/4
1 0 1 SCLK/4
1 1 0 SCLK/8
Output
Rate
Filter
Setup
Length Latency
SCLK 16 Taps
16
SCLK/2 32 Taps
17
SCLK/2 32 Taps
16
SCLK/4 64 Taps
18
SCLK/4 64 Taps
20
SCLK/8 128 Taps
24
SCLK/8 128 Taps
24
Table 3 Single Filter options
the higher frequency components present in the input.
The Nyquist criterion, specifying that the sampling rate
must be at least double the highest frequency compo-
nent, can still then be satisfied even though the sampling
rate has been halved.
The system clock latency for a single device is shown in
Table 3. This is defined as the delay from a particular data
sample being available on the input pins to the first result
including that input appearing on the output pins. It does
not include the delay needed to gather N samples, for an
N tap filter, before a mathematically correct result is
obtained.
DA15:0
F31:0 OEN
NETWORK
A
MUX
DUAL
MODE
NETWORK
B
SINGLE
MODE
DB15:0
X31:0
Figure. 6 Single Filter bus utilisation
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