PDSP16256 Datasheet, PDF (11/28 Pages) Mitel Networks Corporation – Programmable FIR Filter

PDSP16256
Cascading Devices
When the filter requirements are beyond the capabilities
of a single device, it is possible to connect several
devices in cascade increasing the number of taps avail-
able at the required sample rate. Within each device all
filter length, decimate, and bank swap options are still
possible, but each device in the chain must be similarly
programmed and configured as a single filter.
The number of devices which can be cascaded is only
limited by the possibility of overflow in the 32-bit interme-
diate accumulations. If more than sixteen devices are
cascaded in auto EPROM load mode, then an additional
EPROM will be needed.
In modes where the data sample rate does not equal the
clock rate. Then the cascade arrangement shown in Fig.
12 is used. Delayed data is passed from device to device
in one direction, while intermediate results flow in the
opposite direction. The interface device both accepts the
input data and produces the final result. It is not neces-
sary for each device to know its exact position in the
chain, but the device which receives the input data and
produces the final result must be identified, as must the
device which terminates the chain. The former is known
as the Interface device and the latter as the Termination
device, all others are Intermediate devices. Control
Register bits CR11:10 are used to define these positions
as shown in Table 6.
The control logic in each of the devices must be synchro-
nised with respect to the Interface device. This is achieved
by connecting the Delayed Filter Enable output (DFEN)
RESULTS
DATA IN FEN OUT
DA15:0 FEN F31:0
INTERFACE
DEVICE
DB15:0 DFEN X31:0
to the Filter Enable input (FEN) of the next device in the
chain. The Interface device, itself, needs a FEN signal
produced by the system, unless in EPROM mode, where
FRUN may be pulled high. Even when the latter is true,
the FEN connection must be made between the remain-
ing devices in the chain. By effectively extending the
filter length, the cascade latency is therefore the same
as for the single device in the same mode. Once the
pipeline is initially flushed the latency is as given in
Table 3.
When devices are cascaded such that the data sample
rate equals the clock rate, (Control register bits 14:13 =
00), then a different cascade configuration must be
used. This is shown in Fig. 13. The number of devices
that can be cascaded is, again, only limited by the 32-bit
accumulators.
In this mode the delayed data is passed from device to
device in the same direction as the intermediate results.
The device which accepts the input data is now at the
opposite end of the chain to the device which produces
the final result. The control logic in each of the devices
must be synchronised this is achieved by connecting all
the device FEN inputs to the global FEN. The cascade
latency for the complete filter is built up from the 12
delays from the termination device, 8 delays from the
interface device and additional intermediate devices
each adding 4 delays.
Avalable Options
No more than 128 coefficients can be stored internally.
This limits the filter length / decimate / bank swap options
to those which do not require more than that number of
coefficients. Thus when a filter with 128 taps is to be
implemented in a single device, it is not possible to
decimate or bank swap. When a filter with 64 taps is
implemented, decimate or bank swap are possible, but
not both. With all other filter lengths, all decimate and
bank swap configurations are possible.
DA15:0 FEN F31:0
INTERMEDIATE
DEVICE
DB15:0 DFEN X31:0
DA15:0 FEN F31:0
TERMINATION
DEVICE
DB15:0 DFEN X31:0
Figure. 12 Three-device cascaded system
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