PDSP16256 Datasheet, PDF (19/28 Pages) Mitel Networks Corporation – Programmable FIR Filter

PDSP16256
Control Register
The internal operation of the PDSP16256 is
controlled by the status of a 16-bit control register. In
the dual filter modes both networks are controlled by
the same register. The significance of the various
bits are shown in Table 6. Tables 7 and 8 define the
control register bit interdependence for the filter and
bank swapping modes.
The control register is double buffered. This allows
the writing of a new control word without affecting the
current operation of the device. To activate the new
control register after it has been written to the device
the bank swap signal must be toggled. After a reset
the active control register is loaded directly and bank
swap need not be used.
Bits Decode
Function
15
0 Dual filter mode
15
1 Single filter mode
14:13 00 Sample rate is the system clock
14:13 01 Sample rate is half the system clock
14:13 10 Sample rate is quarter the system
clock
14:13 11 Sample rate is eighth the system clock
12
0 Output rate equals the input rate
12
1 Decimate-by-two
11:10 00 Intermediate device
11:10 01 Interface device
11:10 10 Termination device
11:10 11 Single device
9:8
00 These bits MUST be at logical zero
7
0 Bank swap is controlled by input pin
7
1 Bank swap is controlled by Bit 6
6
0 Lower bank if bit 7 is set
6
1 Upper bank if bit 7 is set
5
This bit must be at logical zero
4
0 Two independent filters
4
1 Two filters in cascade
3:0
These bits MUST be at logical zero
Table 6 Control register bit allocation
Control
Register
Bits
15 4
0
0
0
1
1X
Function
Two independent filters
Two filters in cascade
Single Filter
Table 7 Control register filter mode bits
Control
Register
Bits
7
6
5
0X0
1
0
0
1
1
0
XX1
Function
Control by input pin
Lower bank selected
Upper bank selected
Swap on every sample clock
Table 8 Control register bank swap bits
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