MYX4DDR3L128M16JT Datasheet, PDF (46/129 Pages) Micross Components – 8n-bit prefetch architecture

Input Clock Frequency Change
When the DDR3 SDRAM is initialized, the clock must be
stable during most normal states of operation. This means
that after the clock frequency has been set to the stable state,
the clock period is not allowed to deviate, except for what is
allowed by the clock jitter and spread spectrum clocking (SSC)
specifications.
The input clock frequency can be changed from one stable
clock rate to another under two conditions: self refresh mode
and precharge power-down mode. It is illegal to change the
clock frequency outside of those two modes. For the self
refresh mode condition, when the DDR3 SDRAM has been
successfully placed into self refresh mode and ^tCKSRE has
been satisfied, the state of the clock becomes a “Don’t Care.”
When the clock becomes a “Don’t Care,” changing the clock
frequency is permissible if the new clock frequency is stable
prior to ^tCKSRX. When entering and exiting self refresh mode
for the sole purpose of changing the clock frequency, the self
refresh entry and exit specifications must still be met.
The precharge power-down mode condition is when the
DDR3 SDRAM is in precharge power-down mode (either fast
exit mode or slow exit mode). Either ODT must be at a logic
LOW or R_TT,nom and R_TT(WR) must be disabled via MR1 and
MR2. This ensures R_TT,nom and R_TT(WR) are in an off state prior
to entering precharge power-down mode, and CKE must be
at a logic LOW. A minimum of ^tCKSRE must occur after CKE
goes LOW before the clock frequency can change. The DDR3
SDRAM input clock frequency is allowed to change only within
the minimum and maximum operating frequency specified
for the particular speed grade (^tCK [AVG] MIN to ^tCK [AVG]
MAX). During the input clock frequency change, CKE must be
held at a stable LOW level. When the input clock frequency
is changed, a stable clock must be provided to the DRAM
t_{CKSRX before precharge power-down may be exited. After}
precharge power-down is exited and ^tXP has been satisfied,
the DLL must be reset via the MRS. Depending on the new
clock frequency, additional MRS commands may need to be
issued. During the DLL lock time, R_TT,nom and R_TT(WR) must
remain in an off state. After the DLL lock time, the DRAM is
ready to operate with a new clock frequency.
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
46
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
*Advanced information. Subject to change without notice.
Form #: CSI-D-685 Document 009