MYX4DDR3L128M16JT Datasheet, PDF (27/129 Pages) Micross Components – 8n-bit prefetch architecture

2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
Parameter
Data setup time to
DQS, DQS#
Base (specification)
V_REF @ 1 V/ns
Data setup time to
DQS, DQS#
Base (specification)
V_REF @ 1 V/ns
Data setup time to
DQS, DQS#
Base (specification)
V_REF @ 1 V/ns
Data hold time from
DQS, DQS#
Base (specification)
V_REF @ 1 V/ns
Minimum data pulse width
DQS, DQS# to DQ skew, per access
DQ output hold time from DQS, DQS#
DQ Low-Z time from CK, CK#
DQ High-Z time from CK, CK#
DQS, DQS# rising to CK, CK# rising
DQS, DQS# differential input low pulse width
DQS, DQS# differential input high pulse width
DQS, DQS# falling setup to CK, CK# rising
DQS, DQS# falling hold from CK, CK# rising
DQS, DQS# differential WRITE preamble
DQS, DQS# differential WRITE postamble
DQS, DQS# rising to/from rising CK, CK#
DQS, DQS# rising to/from rising CK, CK# when DLL
is disabled
DQS, DQS# differential output high time
DQS, DQS# differential output low time
DQS, DQS# Low-Z time (RL - 1)
DQS, DQS# High-Z time (RL + BL/2)
*Advanced information. Subject to change without notice.
Symbol
DDR3L-1600
Min
Max
DQ Input Timing
–
–
t_{DS (AC175)}
–
–
10
–
t_{DS (AC150)}
160
–
–
–
t_{DS (AC135)}
–
–
45
–
t_{DH (DC100)}
145
–
t_DIPW
360
–
DQ Output Timing
t_DQSQ
–
100
t_QH
0.38
–
t_LZDQ
–450
225
t_HZDQ
–
225
DQ Strobe Input Timing
t_DQSS
–0.27
0.27
t_DQSL
0.45
0.55
t_DQSH
0.45
0.55
t_DSS
0.18
–
t_DSH
0.18
–
t_WPRE
0.9
–
t_WPST
0.3
–
DQ Strobe Output Timing
t_DQSCK
–225
225
t_{DQSCK (DLL_DIS)}
1
10
t_QSH
0.40
–
t_QSL
0.40
–
t_LZDQS
–450
225
t_HZDQS
–
225
Units Notes
ps 18, 19, 44
ps 19, 20
ps 18, 19, 44
ps 19, 20
ps 18, 19
ps 19, 20
ps 18, 19
ps 19, 20
ps
41
ps
t_{CK (AVG) 21}
ps 22, 23
ps 22, 23
CK
25
CK
CK
CK
25
CK
25
CK
CK
ps
23
ns
26
CK
21
CK
21
ps 22, 23
ps 22, 23
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
27
Form #: CSI-D-685 Document 009