MYX4DDR3L128M16JT Datasheet, PDF (1/129 Pages) Micross Components – 8n-bit prefetch architecture

2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
*Advanced information. Subject to change without notice.
2Gbit - 128M x 16 DDR3L SDRAM
Description
The 1.35V DDR3L SDRAM device is a low-voltage version
of the 1.5V DDR3 SDRAM device. Refer to the DDR3 (1.5V)
SDRAM data sheet specifications when running in 1.5V
compatible mode.
Features
• Tin-lead ball metallurgy
• V_DD = V_DDQ = 1.35V (1.283–1.45V)
• Backward-compatible to V_DD = V_DDQ = 1.5V ±0.075V
• Differential bidirectional data strobe
• 8n-bit prefetch architecture
• Differential clock inputs (CK, CK#)
• 8 internal banks
• Nominal and dynamic on-die termination (ODT) for data,
strobe, and mask signals
• Programmable CAS (READ) latency (CL)
• Programmable posted CAS additive latency (AL)
• Programmable CAS (WRITE) latency (CWL)
• Fixed burst length (BL) of 8 and burst chop (BC) of 4 (via
the mode register set [MRS])
• Selectable BC4 or BL8 on-the-fly (OTF)
• Self refresh mode
• T_C of 0°C to +95°C
• 64ms, 8192-cycle refresh at 0°C to +85°C
• 32ms at +85°C to +95°C
• Self refresh temperature (SRT)
• Automatic self refresh (ASR)
• Write leveling
• Multipurpose register
• Output driver calibration
OptionsCode
• Configuration:
• 128 Meg x 16
128M16
• FBGA package (Sn63 / Pb37)
• 96-ball FBGA (8mm x 14mm)
JT
• Timing - cycle time
• 1.25ns @ CL = 11 (DDR3-1600)
-125
• Operating temperature
• Commercial (0°C ≤ T_C ≤ +95°C)
• Industrial (-40°C ≤ T_C ≤ +95°C)
None
IT
Table 1: Key Timing Parameters
Speed Grade Data Rate (MT/s) Target ^tRCD-^tRP-CL ^tRCD (ns) ^tRP (ns) CL (ns)
-125*
1600
11-11-11
13.75
Note: Backward compatible to 1066, CL=7 (-187E) and 1333, CL=9 (-15E)
Table 2: Addressing
Parameter
Configuration
Refresh Count
Row Address
Bank Address
Column Address
128 Meg x 16
16 Meg x 16 x 8 banks
8K
16K A[13:0]
8 BA[2:0]
1K A[9:0]
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
1
Form #: CSI-D-685 Document 009