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| MYX4DDR3L128M16JT Datasheet, PDF (105/129 Pages) Micross Components – 8n-bit prefetch architecture | |||
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FigFuirgeu6r9e: P1R0E4C: HPARREGCEHtAoRPGowE etro-DPoowwneErn-Dtryown Entry
T0
T1
T2
T3
CK#
CK
tCK
tCH
tCL
Command
PRE
NOP
NOP
Address
CKE
All/single
bank
tCPDED
tIS
tPREPDEN
FigFuirgeu7r0e: M10R5S: CMoRmSmCaondmtmo Paonwdetr-oDPowown Eenr-tDryown Entry
T0
T1
T2
Ta0
CK#
CK
tCK
tCH
tCL
Command
MRS
NOP
NOP
NOP
Address
Valid
tMRSPDEN
CKE
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
2Gb: x4, x8, x16 DDR3L SDRAM
Power-Down Mode
*Advanced information. Subject to change without notice.
T4
T5
T6
T7
tPD
Donât Care
Ta1
Ta2
Ta3
Ta4
tCPDED
NOP
NOP
tPD
tIS
Indicates break
in time scale
Donât Care
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
PDF: 09005aef83ed2952
2Gb_DDR3L.pdf - Rev. K 9/13 EN
105
187
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron TechnologyF, oInrcm. A#l:l riCgShIt-s Dre-s6e8r5veDdo. cument 009
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