English
Language : 

MYX4DDR3L128M16JT Datasheet, PDF (30/129 Pages) Micross Components – 8n-bit prefetch architecture
2Gb SDRAM-DDR3L
MYX4DDR3L128M16JT*
Parameter
Minimum CKE low pulse width for self re-fresh entry
to self refresh exit timing
Valid clocks after self refresh entry or power- down
entry
Valid clocks before self refresh exit, power-down exit,
or reset exit
CKE MIN pulse width
Command pass disable delay
Power-down entry to power-down exit timing
Begin power-down period prior to CKE registered
HIGH
Power-down entry period: ODT either synchronous or
asynchronous
Power-down exit period: ODT either synchronous or
asynchronous
ACTIVATE command to power-down entry
PRECHARGE/PRECHARGE ALL command to power-
down entry
REFRESH command to power-down entry
MRS command to power-down entry
READ/READ with auto precharge command to power-
down entry
WRITE command to
power-down entry
WRITE with auto
precharge command
to power-down entry
BL8 (OTF, MRS) BC4OTF
BC4MRS
BL8 (OTF, MRS) BC4OTF
BC4MRS
DLL on, any valid command, or DLL off to commands
not requiring locked DLL
Precharge power-down with DLL off to commands
requiring a locked DLL
*Advanced information. Subject to change without notice.
Symbol
DDR3L-1600
Min
Max
Self Refresh Timing (continued)
tCKESR
MIN = tCKE (MIN) + CK; MAX = N/A
Units Notes
CK
tCKSRE
MIN = greater of 5CK or 10ns; MAX = N/A
CK
tCKSRX
MIN = greater of 5CK or 10ns; MAX = N/A
CK
Power-Down Timing
tCKE (MIN)
Greater of 3CK or 5ns
CK
tCPDED
MIN = 1; MAX = N/A
CK
tPD
MIN = tCKE (MIN); MAX = 9 × tREFI
CK
tANPD
WL - 1CK
CK
PDE
Greater of tANPD or tRFC - REFRESH command to CKE LOW time CK
PDX
tANPD + tXPDLL
Power-Down Entry Minimum Timing
tACTPDEN
MIN = 1
tPRPDEN
MIN = 1
tREFPDEN
tMRSPDEN
MIN = 1
MIN = tMOD (MIN)
tRDPDEN
MIN = RL + 4 + 1
tWRPDEN
MIN = WL + 4 + tWR/tCK (AVG)
tWRPDEN
MIN = WL + 2 + tWR/tCK (AVG)
tWRAP- DEN
MIN = WL + 4 + WR + 1
tWRAP- DEN
MIN = WL + 2 + WR + 1
Power-Down Exit Timing
tXP
MIN = greater of 3CK or 6ns; MAX = N/A
CK
CK
CK
CK
37
CK
CK
CK
CK
CK
CK
CK
tXPDLL
MIN = greater of 10CK or 24ns; MAX = N/A
CK
28
MYX4DDR3L128M16JT*
Revision 1.5 - 10/30/14
30
Form #: CSI-D-685 Document 009