MYX29GL01GS11DPIV2 Datasheet, PDF (42/68 Pages) Micross Components – Tin-lead ball metallurgy

8.2
8.3
8.3.1
8.3.2
1Gb GL-S MirrorBit^® Eclipse^™
Flash Memory
MYX29GL01GS11DPIV2*
*Advanced information. Subject to change without notice.
Power-Off with Hardware Data Protection
The memory is considered to be powered off when the core power supply (V_CC) drops below the lock-out
voltage (V_LKO). When V_CC is below V_LKO, the entire memory array is protected against a program or erase
operation. This ensures that no spurious alteration of the memory content can occur during power transition.
During a power supply transition down to Power-Off, V_IO should remain less than or equal to V_CC.
If V_CC goes below V_RST (Min) then returns above V_RST (Min) to V_CC minimum, the Power-On Reset interface
state is entered and the EAC starts the Cold Reset Embedded Algorithm.
Power Conservation Modes
Interface Standby
Standby is the default, low power, state for the interface while the device is not selected by the host for data
transfer (CE# = High). All inputs are ignored in this state and all outputs except RY/BY# are high impedance.
RY/BY# is a direct output of the EAC, not controlled by the Host Interface.
Automatic Sleep
The automatic sleep mode reduces device interface energy consumption to the sleep level (I_CC6) following the
completion of a random read access time. The device automatically enables this mode when addresses remain
stable for t_ACC + 30 ns. While in sleep mode, output data is latched and always available to the system. Output
of the data depends on the level of the OE# signal but, the automatic sleep mode current is independent of
the OE# signal level. Standard address access timings (t_ACC or t_PACC) provide new data when addresses are
changed. I_CC6 in Section 9.4: DC Characteristics (page 48) represents the automatic sleep mode current
specification.
Automatic sleep helps reduce current consumption especially when the host system clock is slowed for power
reduction. During slow system clock periods, read and write cycles may extend many times their length versus
when the system is operating at high speed. Even though CE# may be Low throughout these extended data
transfer cycles, the memory device host interface will go to the Automatic Sleep current at t_ACC + 30 ns. The
device will remain at the Automatic Sleep current for t_ASSB. Then the device will transition to the standby current
level. This keeps the memory at the Automatic Sleep or standby power level for most of the long duration data
transfer cycles, rather than consuming full read power all the time that the memory device is selected by the
host system.
However, the EAC operates independent of the automatic sleep mode of the host interface and will continue
to draw current during an active Embedded Algorithm. Only when both the host interface and EAC are in their
standby states is the standby level current achieved.
MYX29GL01GS11DPIV2
Revision 1.0 - 01/26/2015
42
Form #: CSI-D-685 Document 001