AX1000-FGG484I Datasheet, PDF (86/262 Pages) Microsemi Corporation – 350+ MHz System Performance, 500+ MHz Internal Performance

Detailed Specifications
The HM and CM modules can select between:
• The HCLK or CLK source respectively
• A local signal routed on generic routing resources
This allows each core tile to have eight clocks independent of the other core tiles in the device.
Both HCLK and CLK are segmentable, meaning that individual branches of the global resource can be
used independently.
Like the HM and CM modules, the HD and RD modules can select between:
• The HCLK or CLK source from the HM or CM module respectively
• A local signal routed on generic routing resources
The AX architecture is capable of supporting a large number of local clocks—24 segments per HCLK
driving north-south and 28 segments per CLK driving east-west per core tile.
Microsemi's Designer software’s place-and-route takes advantage of the segmented clock structure
found in Axcelerator devices by turning off any unused clock segments. This results in not only better
performance but also lower power consumption.
Global Resource Access Macros
Global resources can be driven by one of three sources: external pad(s), an internal net, or the output of
a PLL. These connections can be made by using one of three types of macros: CLKBUF, CLKINT, and
PLLCLK.
CLKBUF and HCLKBUF
CLKBUF (HCLKBUF) is used to drive a CLK (HCLK) from external pads. These macros can be used
either generically or with the specific I/O standard desired (e.g. CLKBUF_LVCMOS25, HCLKBUF_LVDS,
etc.) (Figure 2-42).
P
Clock
Network
N
CLKBUF
HCLKBUF
Figure 2-42 • CLKBUF and HCLKBUF
Package pins CLKEP and CLKEN are associated with CLKE; package pins HCLKAP and HCLKAN are
associated with HCLKA, etc.
Note that when CLKBUF (HCLKBUF) is used with a single-ended I/O standard, it must be tied to the
P-pad of the CLK (HCLK) package pin. In this case, the CLK (HCLK) N-pad can be used for user signals.
CLKINT and HCLKINT
CLKINT (HCLKINT) is used to access the CLK (HCLK) resource internally from the user signals
(Figure 2-43).
Logic
Figure 2-43 • CLKINT and HCLKINT
Clock
Network
CLKINT
HCLKINT
2-72
Revision 18