AX1000-FGG484I Datasheet, PDF (75/262 Pages) Microsemi Corporation – 350+ MHz System Performance, 500+ MHz Internal Performance

Routing Specifications
Axcelerator Family FPGAs
Routing Resources
The routing structure found in Axcelerator devices enables any logic module to be connected to any
other logic module while retaining high performance. There are multiple paths and routing resources that
can be used to route one logic module to another, both within a SuperCluster and elsewhere on the chip.
There are four primary types of routing within the AX architecture: DirectConnect, CarryConnect,
FastConnect, and Vertical and Horizontal Routing.
DirectConnect
DirectConnects provide a high-speed connection between an R-cell and its adjacent C-cell (Figure 2-35).
This connection can be made from DCOUT of the C-cell to DCIN of the R-cell by configuring of the S1
line of the R-cell. This provides a connection that does not require an antifuse and has a delay of less
than 0.1 ns.
Figure 2-35 • DirectConnect and CarryConnect
CarryConnect
CarryConnects are used to build carry chains for arithmetic functions (Figure 2-35). The FCO output of
the right C-cell of a two-C-cell Cluster drives the FCI input of the left C-cell in the two-C-cell Cluster
immediately below it. This pattern continues down both sides of each SuperCluster column.
Similar to the DirectConnects, CarryConnects can be built without an antifuse connection. This
connection has a delay of less than 0.1 ns from the FCO of one two-C-cell cluster to the FCI of the two-
C-cell cluster immediately below it (see the "Carry-Chain Logic" section on page 2-56 for more
information).
FastConnect
For high-speed routing of logic signals, FastConnects can be used to build a short distance connection
using a single antifuse (Figure 2-36 on page 2-62). FastConnects provide a maximum delay of 0.3 ns.
The outputs of each logic module connect directly to the Output Tracks within a SuperCluster. Signals on
the Output Tracks can then be routed through a single antifuse connection to drive the inputs of logic
modules either within one SuperCluster or in the SuperCluster immediately below it.
Revision 18
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