AX1000-FGG484I Datasheet, PDF (66/262 Pages) Microsemi Corporation – 350+ MHz System Performance, 500+ MHz Internal Performance

Detailed Specifications
LVPECL
Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It requires
that one data bit is carried through two signal lines. Like LVDS, two pins are needed. It also requires
external resistor termination. The voltage swing between these two signal lines is approximately 850 mV.
FPGA _P
OUTBUF_LVPECL
100 Ω
100 Ω
N
P
ZO = 50 Ω
187Ω
100 Ω
ZO = 50 Ω
N
FPGA
+
INBUF_LVPECL
–
Figure 2-26 • LVPECL Board-Level Implementation
The LVPECL circuit is similar to the LVDS scheme. It requires four external resistors, three for the driver
and one for the receiver. The values for the three driver resistors are different from that of LVDS since the
output voltage levels are different. Please note that the VOH levels are 200 mV below the standard
LVPECL levels.
Table 2-59 • DC Input and Output Levels
Min.
Typ.
Max.
DC Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Units
VCCI
3
3.3
3.6
V
VOH
1.8
2.11
1.92
2.28
2.13
2.41
V
VOL
0.96
1.27
1.06
1.43
1.3
1.57
V
VIH
1.49
2.72
1.49
2.72
1.49
2.72
V
VIL
0.86
2.125
0.86
2.125
0.86
2.125
V
Differential Input
0.3
0.3
Voltage
0.3
V
Table 2-60 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
1.6 – 0.3
1.6 + 0.3
Note: * Measuring Point = VTRIP
Measuring Point* (V)
1.6
2-52
Revision 18