AX1000-FGG484I Datasheet, PDF (51/262 Pages) Microsemi Corporation – 350+ MHz System Performance, 500+ MHz Internal Performance

Axcelerator Family FPGAs
Timing Characteristics
Table 2-28 • 1.8V LVCMOS I/O Module
Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 1.7 V, TJ = 70°C
–2 Speed
–1 Speed
Std Speed
Parameter
Description
Min. Max. Min. Max. Min. Max.
LVCMOS18 Output Module Timing
t_DP
t_PY
t_ENZL
Input Buffer
Output Buffer
Enable to Pad Delay through the Output
Buffer—Z to Low
3.26
4.55
2.82
3.71
5.18
2.83
4.37
6.09
2.84
t_ENZH
Enable to Pad Delay through the Output
3.43
3.45
3.46
Buffer—Z to High
t_ENLZ
Enable to Pad Delay through the Output
Buffer—Low to Z
6.01
6.85
8.05
t_ENHZ
Enable to Pad Delay through the Output
6.73
7.67
9.01
Buffer—High to Z
t_IOCLKQ
Sequential Clock-to-Q for the I/O Input
Register
0.67
0.77
0.90
t_IOCLKY
Clock-to-output Y for the I/O Output
Register and the I/O Enable Register
0.67
0.77
0.90
t_SUD
t_SUE
t_HD
t_HE
t_CPWHL
t_CPWLH
t_WASYN
t_REASYN
t_HASYN
t_CLR
t_PRESET
Data Input Set-Up
Enable Input Set-Up
Data Input Hold
Enable Input Hold
Clock Pulse Width High to Low
Clock Pulse Width Low to High
Asynchronous Pulse Width
Asynchronous Recovery Time
Asynchronous Removal Time
Asynchronous Clear-to-Q
Asynchronous Preset-to-Q
0.23
0.27
0.31
0.26
0.30
0.35
0.00
0.00
0.00
0.00
0.00
0.00
0.39
0.39
0.39
0.39
0.39
0.39
0.37
0.37
0.37
0.13
0.15
0.17
0.00
0.00
0.00
0.23
0.27
0.31
0.23
0.27
0.31
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Revision 18
2- 37