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AX1000-FGG484I Datasheet, PDF (41/262 Pages) Microsemi Corporation – 350+ MHz System Performance, 500+ MHz Internal Performance | |||
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Axcelerator Family FPGAs
Table 2-22 ⢠3.3 V LVTTL I/O Module
Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, TJ = 70°C (continued)
â2 Speed â1 Speed Std Speed
Parameter
Description
Min. Max. Min. Max. Min. Max. Units
LVTTL Output Drive Strength = 2 (12 mA) / Low Slew Rate
tDP
tPY
tENZL
Input Buffer
Output Buffer
Enable to Pad Delay through the Output BufferâZ to
Low
1.68
12.14
12.43
1.92
13.83
14.16
2.26 ns
16.26 ns
16.65 ns
tENZH
Enable to Pad Delay through the Output BufferâZ to
High
12.17
13.86
16.30 ns
tENLZ
Enable to Pad Delay through the Output BufferâLow
1.73
1.74
1.75 ns
to Z
tENHZ
Enable to Pad Delay through the Output BufferâHigh
2.22
2.23
2.24 ns
to Z
tIOCLKQ
Sequential Clock-to-Q for the I/O Input Register
0.67
0.77
0.90 ns
tIOCLKY
Clock-to-output Y for the I/O Output Register and the
0.67
0.77
0.90 ns
I/O Enable Register
tSUD
tSUE
tHD
tHE
tCPWHL
tCPWLH
tWASYN
tREASYN
tHASYN
tCLR
tPRESET
Data Input Set-Up
Enable Input Set-Up
Data Input Hold
Enable Input Hold
Clock Pulse Width High to Low
Clock Pulse Width Low to High
Asynchronous Pulse Width
Asynchronous Recovery Time
Asynchronous Removal Time
Asynchronous Clear-to-Q
Asynchronous Preset-to-Q
0.23
0.27
0.31 ns
0.26
0.30
0.35 ns
0.00
0.00
0.00 ns
0.00
0.00
0.00 ns
0.39
0.39
0.38
ns
0.39
0.39
0.39
ns
0.37
0.37
0.37
ns
0.13
0.15
0.17 ns
0.00
0.00
0.00 ns
0.23
0.27
0.31 ns
0.23
0.27
0.31 ns
Revision 18
2- 27
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