APA600-PQ208I Datasheet, PDF (78/178 Pages) Microsemi Corporation – ProASICPLUS Flash Family FPGAs

ProASIC^PLUS Flash Family FPGAs
Asynchronous FIFO Write
WB = (WRB + WBLKB)
WDATA
WPE
RB
FULL
EMPTY
EQTH, GETH
Cycle Start
(Full inhibits write)
tWRRDS
tWPDA
tDWRS
tEWRH, tFWRH
tEWRA, tFWRA
tTHWRH
tTHWRA
tWRL
tWRH
tWRCYC
tDWRH
tWPDH
Note: The plot shows the normal operation status.
Figure 2-41 • Asynchronous FIFO Write
Table 2-64 • T_J = 0°C to 110°C; V_DD = 2.3 V to 2.7 V for Commercial/Industrial
T_J = –55°C to 150°C, V_DD = 2.3 V to 2.7 V for Military/MIL-STD-883
Symbol t_xxx
Description
DWRH
DI hold from WB ↑
Min. Max. Units
1.5
ns
DWRS
DI setup to WB ↑
0.5
ns
DWRS
DI setup to WB ↑
2.5
ns
EWRH, FWRH, Old EMPTY, FULL, EQTH, & GETH valid hold
THWRH
time after WB ↑
0.5
ns
EWRA
EMPTY ↓ access from WB ↑
3.0¹
ns
FWRA
New FULL access from WB ↑
3.0¹
ns
THWRA
EQTH or GETH access from WB ↑
4.5
ns
WPDA
WPE access from DI
3.0
ns
WPDH
WPE hold from DI
1.0
ns
WRCYC
WRRDS
Cycle time
RB ↑, clearing FULL, setup to
WB ↓
7.5
ns
3.0²
ns
1.0
WRH
WB high phase
3.0
ns
WRL
WB low phase
3.0
ns
Notes:
1. At fast cycles, EWRA, FWRA = MAX (7.5 ns – WRL), 3.0 ns.
2. At fast cycles, WRRDS (for enabling write) = MAX (7.5 ns – RDL), 3.0 ns.
3. After FIFO reset, WRB needs an initial falling edge prior to any write actions.
Notes
PARGEN is inactive
PARGEN is active
Empty/full/thresh are invalid from the end
of hold until the new access is complete
WPE is invalid while PARGEN is active
Enabling the write operation
Inhibiting the write operation
Inactive
Active
2-68
v5.9