APA600-PQ208I Datasheet, PDF (38/178 Pages) Microsemi Corporation – ProASICPLUS Flash Family FPGAs

ProASIC^PLUS Flash Family FPGAs
Calculating Typical Power Dissipation
ProASIC^PLUS device power is calculated with both a static and an active component. The active component is a function
of both the number of tiles utilized and the system speed. Power dissipation can be calculated using the following
formula:
Total Power Consumption—P_total
P_total = P_dc + P_ac
where:
P_dc = 7 mW for the APA075
8 mW for the APA150
11 mW for the APA300
12 mW for the APA450
12 mW for the APA600
13 mW for the APA750
19 mW for the APA1000
P_dc includes the static components of P_VDDP + P_VDD + P_AVDD
P_ac = P_clock + P_storage + P_logic + P_outputs + P_inputs + P_pll + P_memory
Global Clock Contribution—P_clock
P_clock, the clock component of power dissipation, is given by the piece-wise model:
for R < 15000 the model is: (P1 + (P2*R) – (P7*R2)) * Fs (lightly-loaded clock trees)
for R > 15000 the model is: (P10 + P11*R) * Fs (heavily-loaded clock trees)
where:
P1 = ^{100 µW/MHz is the basic power consumption of the clock tree per MHz of the clock}
P2 = ^{1.3 µW/MHz is the incremental power consumption of the clock tree per storage tile – also per MHz of the}
clock
P7 = ^{0.00003 µW/MHz is a correction factor for partially-loaded clock trees}
P10 = ^{6850 µW/MHz is the basic power consumption of the clock tree per MHz of the clock}
P11 = ^{0.4 µW/MHz is the incremental power consumption of the clock tree per storage tile – also per MHz of}
the clock
R = ^{the number of storage tiles clocked by this clock}
Fs = ^{the clock frequency}
Storage-Tile Contribution—P_storage
P_storage, the storage-tile (Register) component of AC power dissipation, is given by
P_storage = P5 * ms * Fs
where:
P5 = 1.1 µW/MHz is the average power consumption of a storage tile per MHz of its output toggling rate.
The maximum output toggling rate is Fs/2.
ms = the number of storage tiles (Register) switching during each Fs cycle
Fs = the clock frequency
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