APA600-PQ208I Datasheet, PDF (31/178 Pages) Microsemi Corporation – ProASICPLUS Flash Family FPGAs

Table 2-13 • Basic Memory Configurations
Type
Write Access
Read Access
RAM
Asynchronous
Asynchronous
RAM
Asynchronous
Asynchronous
RAM
Asynchronous
Synchronous Transparent
RAM
Asynchronous
Synchronous Transparent
RAM
Asynchronous
Synchronous Pipelined
RAM
Asynchronous
Synchronous Pipelined
RAM
Synchronous
Asynchronous
RAM
Synchronous
Asynchronous
RAM
Synchronous
Synchronous Transparent
RAM
Synchronous
Synchronous Transparent
RAM
Synchronous
Synchronous Pipelined
RAM
Synchronous
Synchronous Pipelined
FIFO
Asynchronous
Asynchronous
FIFO
Asynchronous
Asynchronous
FIFO
Asynchronous
Synchronous Transparent
FIFO
Asynchronous
Synchronous Transparent
FIFO
Asynchronous
Synchronous Pipelined
FIFO
Asynchronous
Synchronous Pipelined
FIFO
Synchronous
Asynchronous
FIFO
Synchronous
Asynchronous
FIFO
Synchronous
Synchronous Transparent
FIFO
Synchronous
Synchronous Transparent
FIFO
Synchronous
Synchronous Pipelined
FIFO
Synchronous
Synchronous Pipelined
ProASIC^PLUS Flash Family FPGAs
Parity
Checked
Generated
Checked
Generated
Checked
Generated
Checked
Generated
Checked
Generated
Checked
Generated
Checked
Generated
Checked
Generated
Checked
Generated
Checked
Generated
Checked
Generated
Checked
Generated
Library Cell Name
RAM256x9AA
RAM256x9AAP
RAM256x9AST
RAM256x9ASTP
RAM256x9ASR
RAM256x9ASRP
RAM256x9SA
RAM256xSAP
RAM256x9SST
RAM256x9SSTP
RAM256x9SSR
RAM256x9SSRP
FIFO256x9AA
FIFO256x9AAP
FIFO256x9AST
FIFO256x9ASTP
FIFO256x9ASR
FIFO256x9ASRP
FIFO256x9SA
FIFO256x9SAP
FIFO256x9SST
FIFO256x9SSTP
FIFO256x9SSR
FIFO256x9SSRP
v5.9
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