A3PE600L-FGG484M Datasheet, PDF (35/212 Pages) Microsemi Corporation – Each Device Tested from –55°C to 125°C, Not Susceptible to Neutron-Induced Configuration Loss

PAD
Military ProASIC3/EL Low Power Flash FPGAs
t_PY
t_DIN
DQ
Y
DIN
CLK
To Array
t_PY = MAX(t_PY(R), t_PY(F))
t_DIN = MAX(t_DIN(R), t_DIN(F))
I/O Interface
VIH
PAD
V_trip
V_trip
VIL
VCC
Y
GND
50%
t_PY
(R)
50%
t_PY
(F)
DIN
GND
50%
t_DOUT
(R)
VCC
t_DOUT
(F)
Figure 2-5 • Input Buffer Timing Model and Delays (example)
50%
Revision 3
2- 21