A3PE600L-FGG484M Datasheet, PDF (165/212 Pages) Microsemi Corporation – Each Device Tested from –55°C to 125°C, Not Susceptible to Neutron-Induced Configuration Loss

3 – Pin Descriptions and Packaging
Supply Pins
GND
Ground
Ground supply voltage to the core, I/O outputs, and I/O logic.
GNDQ
Ground (quiet)
Quiet ground supply voltage to input buffers of I/O banks. Within the package, the GNDQ plane is
decoupled from the simultaneous switching noise originated from the output buffer ground domain. This
minimizes the noise transfer within the package and improves input signal integrity. GNDQ must always
be connected to GND on the board.
VCC
Core Supply Voltage
Supply voltage to the FPGA core, nominally 1.5 V for A3P250 and A3P100 devices and 1.2 V or 1.5 V for
A3PE600L and A3PE3000L devices. VCC is required for powering the JTAG state machine in addition to
VJTAG. Even when a device is in bypass mode in a JTAG chain of interconnected devices, both VCC
and VJTAG must remain powered to allow JTAG signals to pass through the device.
For A3PE600L and A3PE3000L devices, VCC can be switched dynamically from 1.2 V to 1.5 V or vice
versa. This allows in-system programming (ISP) when VCC is at 1.5 V and the benefit of low power
operation when VCC is at 1.2 V.
VCCIBx
I/O Supply Voltage
Supply voltage to the bank's I/O output buffers and I/O logic. Bx is the I/O bank number. There are up to
eight I/O banks on low power flash devices plus a dedicated VJTAG bank. Each bank can have a
separate VCCI connection. All I/Os in a bank will run off the same VCCIBx supply. VCCI can be 1.5 V,
1.8 V, 2.5 V, or 3.3 V, nominal voltage. Unused I/O banks should have their corresponding VCCI pins tied
to GND.
VMVx
I/O Supply Voltage (quiet)
Quiet supply voltage to the input buffers of each I/O bank. x is the bank number. Within the package, the
VMV plane is decoupled from the simultaneous switching noise originating from the output buffer V_CCI
domain. This minimizes the noise transfer within the package and improves input signal integrity. Each
bank must have at least one VMV connection, and no VMV should be left unconnected. All I/Os in a bank
run off the same VMVx supply. VMV is used to provide a quiet supply voltage to the input buffers of each
I/O bank. VMVx can be 1.2 V (A3PE600L and A3PE3000L only), 1.5 V, 1.8 V, 2.5 V, or 3.3 V, nominal
voltage. Unused I/O banks should have their corresponding VMV pins tied to GND. VMV and VCCI should
be at the same voltage within a given I/O bank. Used VMV pins must be connected to the corresponding
VCCI pins of the same bank (i.e., VMV0 to VCCIB0, VMV1 to VCCIB1, etc.).
VCCPLA/B/C/D/E/F
PLL Supply Voltage
Supply voltage to analog PLL, nominally 1.5 V or 1.2 V, depending on the device.
• 1.5 V for A3P250 and A3P1000 devices
• 1.2 V or 1.5 V for A3PE600L or A3PE3000L devices
When the PLLs are not used, the Microsemi Designer place-and-route tool automatically disables the
unused PLLs to lower power consumption. The user should tie unused VCCPLx and VCOMPLx pins to
ground. Microsemi recommends tying VCCPLx to VCC and using proper filtering circuits to decouple
VCC noise from the PLLs. Refer to the PLL Power Supply Decoupling section of the "Clock Conditioning
Circuits in Low Power Flash Devices and Mixed Signal FPGAs" chapter of the Miliary ProASIC3/EL
Device Family User’s Guide for a complete board solution for the PLL analog power supply and ground.
• There is one VCCPLF pin on A3P250 and A3P1000 devices.
• There are six VCCPLX pins on A3PE600L and A3PE3000L devices.
Revision 3
3-1