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HAL805 Datasheet, PDF (19/24 Pages) Micronas – Programmable Linear Hall Effect Sensor
PRELIMINARY DATA SHEET
HAL 805
5. Programming of the Sensor
5.1. Definition of Programming Pulses
The sensor is addressed by modulating a serial tele-
gram on the supply voltage. The sensor answers with
a serial telegram on the output pin.
The bits in the serial telegram have a different bit time
for the VDD-line and the output. The bit time for the
VDD-line is defined through the length of the Sync Bit
at the beginning of each telegram. The bit time for the
output is defined through the Acknowledge Bit.
A logical “0” is coded as no voltage change within the
bit time. A logical “1” is coded as a voltage change
between 50% and 80% of the bit time. After each bit, a
voltage change occurs.
5.2. Definition of the Telegram
Each telegram starts with the Sync Bit (logical 0), 3
bits for the Command (COM), the Command Parity Bit
(CP), 4 bits for the Address (ADR), and the Address
Parity Bit (AP).
There are 4 kinds of telegrams:
– Write a register (see Fig. 5–2)
After the AP Bit, follow 14 Data Bits (DAT) and the
Data Parity Bit (DP). If the telegram is valid and the
command has been processed, the sensor answers
with an Acknowledge Bit (logical 0) on the output.
– Read a register (see Fig. 5–3)
After evaluating this command, the sensor answers
with the Acknowledge Bit, 14 Data Bits, and the
Data Parity Bit on the output.
– Programming the EEPROM cells (see Fig. 5–4)
After evaluating this command, the sensor answers
with the Acknowledge Bit. After the delay time tw,
the supply voltage rises up to the programming volt-
age.
– Activate a sensor (see Fig. 5–5))
If more than one sensor is connected to the supply
line, selection can be done by first deactivating all
sensors. The output of all sensors will be pulled to
ground by the internal 10 kΩ resistors. With an Acti-
vate pulse on the appropriate output pin, an individ-
ual sensor can be selected. All following commands
will only be accepted from the activated sensor.
tr
tf
VDDH
logical 0
tp0
or
tp0
VDDL
VDDH
logical 1
VDDL
tp0
tp1
tp1
or
tp0
Fig. 5–1: Definition of logical 0 and 1 bit
Table 5–1: Telegram parameters
Symbol
VDDL
VDDH
tr
tf
tp0
tpOUT
Parameter
Supply Voltage for Low Level
during Programming
Supply Voltage for High Level
during Programming
Rise time
Fall time
Bit time on VDD
Bit time on output pin
tp1
VDDPROG
tPROG
Voltage Change for logical 1
Supply Voltage for
Programming the EEPROM
Programming Time for EEPROM
Micronas
Pin
Min. Typ. Max. Unit
Remarks
1
5
5.6
6
V
1
6.8
8.0
8.5
V
1
0.05 ms
1
0.05 ms
1
1.7
1.75 1.8
ms
3
2
3
4
ms
1, 3
50
65
1
11.95 12
80
%
12.1 V
tp0 is defined through the Sync Bit
tpOUT is defined through the
Acknowledge Bit
% of tp0 or tpOUT
1
95
100
105
ms
19