MT48LC64M4A2_12 Datasheet, PDF (85/86 Pages) Micron Technology – SDR SDRAM

256Mb: x4, x8, x16 SDRAM
Clock Suspend
Figure 56: Clock Suspend During READ Burst
T0
T1
T2
T3
T4
T5
T6
CLK
CKE
Internal
clock
Command
READ
NOP
NOP
NOP
NOP
NOP
Address
Bank,
Col n
DQ
D_OUT
D_OUT
D_OUT
D_OUT
Don’t Care
Note: 1. For this example, CL = 2, BL = 4 or greater, and DQM is LOW.
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. R 10/12 EN
85
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