MT48LC64M4A2_12 Datasheet, PDF (31/86 Pages) Micron Technology – SDR SDRAM

256Mb: x4, x8, x16 SDRAM
Commands
Commands
The following table provides a quick reference of available commands, followed by a
written description of each command. Additional Truth Tables (Table 15 (page 37), Ta-
ble 16 (page 39), and Table 17 (page 41)) provide current state/next state informa-
tion.
Table 14: Truth Table – Commands and DQM Operation
Note 1 applies to all parameters and conditions
Name (Function)
COMMAND INHIBIT (NOP)
NO OPERATION (NOP)
ACTIVE (select bank and activate row)
READ (select bank and column, and start READ burst)
WRITE (select bank and column, and start WRITE burst)
BURST TERMINATE
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH (enter self refresh mode)
LOAD MODE REGISTER
Write enable/output enable
Write inhibit/output High-Z
CS# RAS# CAS# WE# DQM ADDR DQ Notes
HX
XXX
X
X
LH
HHX
X
X
LL
H H X Bank/row X
2
LH
L
H L/H Bank/col X
3
LH
L
L L/H Bank/col Valid 3
LH
H
LX
X
Active 4
LL
H
L
X
Code
X
5
LL
L
HX
X
X
6, 7
LL
L
L X Op-code X
8
XX
XXL
X
Active 9
XX
X XH
X
High-Z 9
Notes:
1. CKE is HIGH for all commands shown except SELF REFRESH.
2. A[0:n] provide row address (where An is the most significant address bit), BA0 and BA1
determine which bank is made active.
3. A[0:i] provide column address (where i = the most significant column address for a given
device configuration). A10 HIGH enables the auto precharge feature (nonpersistent),
while A10 LOW disables the auto precharge feature. BA0 and BA1 determine which
bank is being read from or written to.
4. The purpose of the BURST TERMINATE command is to stop a data burst, thus the com-
mand could coincide with data on the bus. However, the DQ column reads a “Don’t
Care” state to illustrate that the BURST TERMINATE command can occur when there is
no data present.
5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: all banks pre-
charged and BA0, BA1 are “Don’t Care.”
6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” ex-
cept for CKE.
8. A[11:0] define the op-code written to the mode register.
9. Activates or deactivates the DQ during WRITEs (zero-clock delay) and READs (two-clock
delay).
COMMAND INHIBIT
The COMMAND INHIBIT function prevents new commands from being executed by
the device, regardless of whether the CLK signal is enabled. The device is effectively de-
selected. Operations already in progress are not affected.
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