MT48LC64M4A2_12 Datasheet, PDF (83/86 Pages) Micron Technology – SDR SDRAM

Power-Down
256Mb: x4, x8, x16 SDRAM
Power-Down
Power-down occurs if CKE is registered LOW coincident with a NOP or COMMAND IN-
HIBIT when no accesses are in progress. If power-down occurs when all banks are idle,
this mode is referred to as precharge power-down; if power-down occurs when there is a
row active in any bank, this mode is referred to as active power-down. Entering power-
down deactivates the input and output buffers, excluding CKE, for maximum power
savings while in standby. The device cannot remain in the power-down state longer
than the refresh period (64ms) because no REFRESH operations are performed in this
mode.
The power-down state is exited by registering a NOP or COMMAND INHIBIT with CKE
HIGH at the desired clock edge (meeting ^tCKS).
Figure 54: Power-Down Mode
T0
CLK
T1
tCK
T2
tCL
tCH
tCKS
((
))
((
))
CKE
((
tCKS tCKH
))
tCMS tCMH
((
Command PRECHARGE
NOP
NOP
))
((
))
((
DQM
))
((
))
Tn + 1
tCKS
Tn + 2
NOP
ACTIVE
Address
A10
BA0, BA1
All banks
Single bank
tAS tAH
Bank(s)
((
))
((
Row
))
((
))
((
Row
))
((
))
((
Bank
))
DQ ^High-Z
Precharge all
active banks
Two clock cycles
All banks idle, enter
power-down mode
((
))
Input buffers gated off
while in power-down mode
Exit power-down mode
All banks idle
Don’t Care
Note: 1. Violating refresh requirements during power-down may result in a loss of data.
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. R 10/12 EN
83
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