MT48LC16M16A2P-75DTR Datasheet, PDF (67/86 Pages) Micron Technology – SDR SDRAM MT48LC64M4A2 – 16 Meg x 4 x 4 banks MT48LC32M8A2 – 8 Meg x 8 x 4 banks MT48LC16M16A2 – 4 Meg x 16 x 4 banks

256Mb: x4, x8, x16 SDRAM
PRECHARGE Operation
PRECHARGE Operation
The PRECHARGE command (see Figure 17 (page 35)) is used to deactivate the open row
in a particular bank or the open row in all banks. The bank(s) will be available for a sub-
sequent row access some specified time (^tRP) after the PRECHARGE command is is-
sued. Input A10 determines whether one or all banks are to be precharged, and in the
case where only one bank is to be precharged (A10 = LOW), inputs BA0 and BA1 select
the bank. When all banks are to be precharged (A10 = HIGH), inputs BA0 and BA1 are
treated as “Don’t Care.” After a bank has been precharged, it is in the idle state and
must be activated prior to any READ or WRITE commands being issued to that bank.
Auto Precharge
Auto precharge is a feature that performs the same individual-bank PRECHARGE func-
tion described previously, without requiring an explicit command. This is accomplished
by using A10 to enable auto precharge in conjunction with a specific READ or WRITE
command. A precharge of the bank/row that is addressed with the READ or WRITE
command is automatically performed upon completion of the READ or WRITE burst,
except in the continuous page burst mode where auto precharge does not apply. In the
specific case of write burst mode set to single location access with burst length set to
continuous, the burst length setting is the overriding setting and auto precharge does
not apply. Auto precharge is nonpersistent in that it is either enabled or disabled for
each individual READ or WRITE command.
Auto precharge ensures that the precharge is initiated at the earliest valid stage within a
burst. Another command cannot be issued to the same bank until the precharge time
(^tRP) is completed. This is determined as if an explicit PRECHARGE command was is-
sued at the earliest possible time, as described for each burst type in the Burst Type
(page 46) section.
Micron SDRAM supports concurrent auto precharge; cases of concurrent auto pre-
charge for READs and WRITEs are defined below.
READ with auto precharge interrupted by a READ (with or without auto precharge)
A READ to bank m will interrupt a READ on bank n following the programmed CAS la-
tency. The precharge to bank n begins when the READ to bank m is registered (see Fig-
ure 40 (page 68)).
READ with auto precharge interrupted by a WRITE (with or without auto precharge)
A WRITE to bank m will interrupt a READ on bank n when registered. DQM should be
used two clocks prior to the WRITE command to prevent bus contention. The pre-
charge to bank n begins when the WRITE to bank m is registered (see Figure 41
(page 69)).
WRITE with auto precharge interrupted by a READ (with or without auto precharge)
A READ to bank m will interrupt a WRITE on bank n when registered, with the data-out
appearing CL later. The precharge to bank n will begin after ^tWR is met, where ^tWR be-
gins when the READ to bank m is registered. The last valid WRITE to bank n will be da-
ta-in registered one clock prior to the READ to bank m (see Figure 46 (page 74)).
WRITE with auto precharge interrupted by a WRITE (with or without auto precharge)
A WRITE to bank m will interrupt a WRITE on bank n when registered. The precharge to
bank n will begin after ^tWR is met, where ^tWR begins when the WRITE to bank m is reg-
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. U 05/13 EN
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© 1999 Micron Technology, Inc. All rights reserved.