|
MT48LC16M16A2P-75DTR Datasheet, PDF (1/86 Pages) Micron Technology – SDR SDRAM MT48LC64M4A2 – 16 Meg x 4 x 4 banks MT48LC32M8A2 – 8 Meg x 8 x 4 banks MT48LC16M16A2 – 4 Meg x 16 x 4 banks | |||
|
SDR SDRAM
MT48LC64M4A2 â 16 Meg x 4 x 4 banks
MT48LC32M8A2 â 8 Meg x 8 x 4 banks
MT48LC16M16A2 â 4 Meg x 16 x 4 banks
256Mb: x4, x8, x16 SDRAM
Features
Features
⢠PC100- and PC133-compliant
⢠Fully synchronous; all signals registered on positive
edge of system clock
⢠Internal, pipelined operation; column address can
be changed every clock cycle
⢠Internal banks for hiding row access/precharge
⢠Programmable burst lengths: 1, 2, 4, 8, or full page
⢠Auto precharge, includes concurrent auto precharge
and auto refresh modes
⢠Self refresh mode (not available on AT devices)
⢠Auto refresh
â 64ms, 8192-cycle refresh (commercial and
industrial)
â 16ms, 8192-cycle refresh (automotive)
⢠LVTTL-compatible inputs and outputs
⢠Single 3.3V ±0.3V power supply
Options
⢠Configurations
â 64 Meg x 4 (16 Meg x 4 x 4 banks)
â 32 Meg x 8 (8 Meg x 8 x 4 banks)
â 16 Meg x 16 (4 Meg x 16 x 4 banks)
⢠Write recovery (tWR)
â tWR = 2 CLK
⢠Plastic package â OCPL1
â 54-pin TSOP II OCPL1 (400 mil)
(standard)
â 54-pin TSOP II OCPL1 (400 mil)
Pb-free
Marking
64M4
32M8
16M16
A2
TG
P
Options
Marking
â 60-ball TFBGA (x4, x8) (8mm x
FB
16mm)
â 60-ball TFBGA (x4, x8) (8mm x
BB
16mm) Pb-free
â 54-ball VFBGA (x16) (8mm x 14 mm)
FG2
â 54-ball VFBGA (x16) (8mm x 14 mm)
BG2
Pb-free
â 54-ball VFBGA (x16) (8mm x 8 mm)
F43
â 54-ball VFBGA (x16) (8mm x 8 mm)
B43
Pb-free
⢠Timing â cycle time
â 6ns @ CL = 3 (x8, x16 only)
-6A
â 7.5ns @ CL = 3 (PC133)
-752
â 7.5ns @ CL = 2 (PC133)
-7E
⢠Self refresh
â Standard
â Low power
None
L2, 4
⢠Operating temperature range
â Commercial (0ËC to +70ËC)
None
â Industrial (â40ËC to +85ËC)
IT
â Automotive (â40ËC to +105ËC)
AT4
⢠Revision
:D/:G
Notes:
1. Off-center parting line.
2. Only available on Revision D.
3. Only available on Revision G.
4. Contact Micron for availability.
Table 1: Key Timing Parameters
CL = CAS (READ) latency
Clock
Speed Grade
Frequency (MHz)
-6A
167
-75
133
-7E
133
Target tRCD-tRP-CL
3-3-3
3-3-3
2-2-2
tRCD (ns)
18
20
15
tRP (ns)
18
20
15
CL (ns)
18
20
15
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. U 05/13 EN
1
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 1999 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
|
▷ |