MT46H16M16LFBF-6ITH Datasheet, PDF(67/79 Page) Micron Technology – Mobile DDR SDRAM MT46H16M16LF – 4 Meg x 16 x 4 banks MT46H8M32LF/LG

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MT46H16M16LFBF-6ITH Datasheet, PDF (67/79 Pages) Micron Technology – Mobile DDR SDRAM MT46H16M16LF – 4 Meg x 16 x 4 banks MT46H8M32LF/LG – 2 Meg x 32 x 4 banks

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256Mb: x16, x32 Mobile DDR SDRAM

Timing Diagrams

Figure 38: Data Output Timing â tDQSQ, tQH, and Data Valid Window (x32)

CK#

tHP5

DQM0/DQM1/DQM2/DQM3

DQ (Last data valid)2

DQ2

DQ (First data no longer valid)2

DQ (Last data valid)2

DQ (First data no longer valid)2

DQ and DQS collectively6

T2n

T3n

tHP5

tDQSQ3

tHP5

tDQSQ3

tHP5

tDQSQ3

tQH4

T2n

tQH4

T3n

Data valid Data valid Data valid

window window

window

Data valid

window

Notes:

1. DQ transitioning after DQS transitions defines the tDQSQ window.

2. Byte 0 is DQ[7:0]; byte 1 is DQ[15:8]; byte 2 is DQ[23:16]; byte 3 is DQ[31:24].

3. tDQSQ is derived at each DQS clock edge and is not cumulative over time and begins with

DQS transition and ends with the last valid DQ transition.

4. tQH is derived from tHP: tQH = tHP - tQHS.

5. tHP is the lesser of tCL or tCH clock transition collectively when a bank is active.

6. The data valid window is derived for each DQS transition and is tQH - tDQSQ.

PDF: 09005aef82091978 / Source: 09005aef8209195b

MT46H16M16LF__2.fm - Rev. H 6/08 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

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