MT46H16M16LFBF-6ITH Datasheet, PDF (64/79 Pages) Micron Technology – Mobile DDR SDRAM MT46H16M16LF – 4 Meg x 16 x 4 banks MT46H8M32LF/LG – 2 Meg x 32 x 4 banks

256Mb: x16, x32 Mobile DDR SDRAM
Notes
16. MIN (^tRC or ^tRFC) for IDD measurements is the smallest multiple of ^tCK that meets
the minimum absolute value for the respective parameter.
17. The I/O capacitance per DQS and DQ byte/group will not differ by more than this
maximum amount for any given device.
18. The data valid window is derived by achieving other specifications: ^tHP (^tCK/2),
t_{DQSQ, and} t_{QH (}t_{QH =} t_{HP -} t_{QHS). The data valid window derates in direct propor-}
tion to the clock duty cycle, and a practical data valid window can be derived. The
clock is allowed a maximum duty cycle variation of 45/55. Functionality is uncertain
when operating beyond a 45/55 ratio.
19. Referenced to each output group: for x16, LDQS with DQ0–DQ7; and UDQS with
DQ8–DQ15. For x32, DQS0 with DQ0–DQ7; DQS1 with DQ8–DQ15; DQS2 with DQ16–
DQ23; and DQS3 with DQ24–DQ31.
20. This limit is actually a nominal value and does not result in a fail value. CKE is HIGH
during REFRESH command period (^tRFC [MIN]) else CKE is LOW (for example,
during standby).
21. To maintain a valid level, the transitioning edge of the input must:
a. Sustain a constant slew rate from the current AC level through to the target AC
level, VIL(AC) or VIH(AC).
b. Reach at least the target AC level.
c. After the AC target level is reached, continue to maintain at least the target DC
level, VIL(DC) or VIH(DC).
22. CK and CK# input slew rate must be ≥1 V/ns (2 V/ns if measured differentially).
23. DQ and DM input slew rates must not deviate from DQS by more than 10 percent. If
the DQ/DM/DQS slew rate is less than 0.5 V/ns, timing must be derated: 50ps must
be added to ^tDS and ^tDH for each 100 mV/ns reduction in slew rate. If slew rate
exceeds 4 V/ns, functionality is uncertain.
24. ^tHP (MIN) is the lesser of ^tCL minimum and ^tCH minimum actually applied to the
device CK and CK# inputs, collectively.
25. READs and WRITEs with auto precharge are not allowed to be issued until ^tRAS (MIN)
can be satisfied prior to the internal PRECHARGE command being issued.
26. Any positive glitch must be less than 1/3 of the clock cycle and not more than +200mV
or 2.0V, whichever is less. Any negative glitch must be less than 1/3 of the clock cycle
and not exceed either –150mV or 1.6V, whichever is more positive.
27. The voltage levels used are derived from a minimum VDD level and the referenced
test load. In practice, the voltage levels obtained from a properly terminated bus
will provide significantly different voltage values.
28. VIH overshoot: VIH (MAX) = VDDQ + 1.0V for a pulse width ≤3ns, and the pulse width
cannot be greater than 1/3 of the cycle rate. VIL undershoot: VIL (MIN) = –1.0V for a
pulse width ≤3ns, and the pulse width cannot be greater than 1/3 of the cycle rate.
29. VDD and VDDQ must track each other, and VDDQ must be less than or equal to VDD.
30. ^tHZ (MAX) will prevail over ^tDQSCK (MAX) + ^tRPST (MAX) condition.
31. The transition times for input signals (CAS#, CKE, CS#, DM, DQ, DQS, RAS#, WE#,
and addresses) are measured between VIL(DC) and VIH(AC) for rising input signals and
between VIH(DC) and VIL(AC) for falling input signals.
32. ^tDAL = (^tWR/^tCK) + (^tRP/^tCK): for each term, if not already an integer, round to the
next higher integer.
33. These parameters guarantee device timing, but are not tested on each device.
34. Clock must be toggled a minimum of two times during this period.
PDF: 09005aef82091978 / Source: 09005aef8209195b
MT46H16M16LF__2.fm - Rev. H 6/08 EN
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